Lines Matching refs:status
168 int status = INTEL_SIP_SMC_STATUS_OK;
174 status = mailbox_read_response(job_id,
177 if (status < 0) {
192 if (status != MBOX_NO_RESPONSE &&
193 status != MBOX_TIMEOUT && resp_len != 0) {
205 status = INTEL_SIP_SMC_STATUS_OK;
207 status = INTEL_SIP_SMC_STATUS_BUSY;
221 return status;
228 int status = 0;
238 status = mailbox_send_fpga_config_comp();
240 if (status < 0) {
266 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size,
269 if (status < 0) {
633 int status;
637 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U,
640 if (status < 0) {
665 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent,
668 if (status < 0) {
669 *mbox_status = -status;
683 int status;
686 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL,
689 if (status < 0) {
700 int status = 0;
712 status = mailbox_read_response_async(job_id,
715 status = mailbox_read_response(job_id,
718 if (status == MBOX_NO_RESPONSE) {
719 status = MBOX_BUSY;
723 if (status == MBOX_NO_RESPONSE) {
727 if (status == MBOX_BUSY) {
734 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 ||
735 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) {
736 *mbox_error = -status;
737 } else if (status != MBOX_RET_OK) {
738 *mbox_error = -status;
748 int status = 0;
752 status = socfpga_bridges_enable((uint32_t)mask);
754 status = socfpga_bridges_enable(~0);
758 status = socfpga_bridges_disable((uint32_t)mask);
760 status = socfpga_bridges_disable(~0);
764 if (status < 0) {
1100 int status = 0;
1124 status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
1128 /* Always reserve [0] index for command status. */
1129 ret_args[0] = status;
1142 status = mailbox_response_poll_on_intr_v3(&client_id,
1146 SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1],
1153 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1163 SMC_RET1(handle, status);
1168 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1178 SMC_RET1(handle, status);
1183 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1193 SMC_RET1(handle, status);
1198 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1208 SMC_RET1(handle, status);
1222 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1232 SMC_RET1(handle, status);
1244 status = INTEL_SIP_SMC_STATUS_REJECTED;
1245 SMC_RET1(handle, status);
1252 status = INTEL_SIP_SMC_STATUS_REJECTED;
1253 SMC_RET1(handle, status);
1258 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1268 SMC_RET1(handle, status);
1281 status = INTEL_SIP_SMC_STATUS_REJECTED;
1282 SMC_RET1(handle, status);
1288 status = INTEL_SIP_SMC_STATUS_REJECTED;
1289 SMC_RET1(handle, status);
1292 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1302 SMC_RET1(handle, status);
1313 status = INTEL_SIP_SMC_STATUS_REJECTED;
1314 SMC_RET1(handle, status);
1319 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1329 SMC_RET1(handle, status);
1336 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1346 SMC_RET1(handle, status);
1356 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1366 SMC_RET1(handle, status);
1371 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1381 SMC_RET1(handle, status);
1386 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1396 SMC_RET1(handle, status);
1403 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1413 SMC_RET1(handle, status);
1427 status = INTEL_SIP_SMC_STATUS_REJECTED;
1428 SMC_RET1(handle, status);
1435 status = INTEL_SIP_SMC_STATUS_REJECTED;
1436 SMC_RET1(handle, status);
1445 status = INTEL_SIP_SMC_STATUS_REJECTED;
1446 SMC_RET1(handle, status);
1456 status = INTEL_SIP_SMC_STATUS_REJECTED;
1457 SMC_RET1(handle, status);
1461 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1471 SMC_RET1(handle, status);
1486 status = INTEL_SIP_SMC_STATUS_REJECTED;
1487 SMC_RET1(handle, status);
1495 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1504 SMC_RET1(handle, status);
1509 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1518 SMC_RET1(handle, status);
1523 status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3,
1525 SMC_RET1(handle, status);
1530 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1539 SMC_RET1(handle, status);
1544 status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
1546 SMC_RET1(handle, status);
1551 status = intel_fcs_create_cert_on_reload(smc_fid, x1,
1553 SMC_RET1(handle, status);
1559 status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3,
1563 status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3,
1568 status = INTEL_SIP_SMC_STATUS_REJECTED;
1570 SMC_RET1(handle, status);
1575 status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error);
1576 SMC_RET1(handle, status);
1581 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1590 SMC_RET1(handle, status);
1597 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1606 SMC_RET1(handle, status);
1618 status = INTEL_SIP_SMC_STATUS_REJECTED;
1619 SMC_RET1(handle, status);
1622 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1631 SMC_RET1(handle, status);
1641 status = INTEL_SIP_SMC_STATUS_REJECTED;
1642 SMC_RET1(handle, status);
1645 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1654 SMC_RET1(handle, status);
1666 status = INTEL_SIP_SMC_STATUS_REJECTED;
1667 SMC_RET1(handle, status);
1673 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1682 SMC_RET1(handle, status);
1693 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1702 SMC_RET1(handle, status);
1714 status = INTEL_SIP_SMC_STATUS_REJECTED;
1715 SMC_RET1(handle, status);
1721 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1730 SMC_RET1(handle, status);
1735 status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
1737 SMC_RET1(handle, status);
1747 status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2,
1750 SMC_RET1(handle, status);
1755 status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
1757 SMC_RET1(handle, status);
1766 status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2,
1770 SMC_RET1(handle, status);
1775 status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6,
1777 SMC_RET1(handle, status);
1786 status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2,
1789 SMC_RET1(handle, status);
1794 status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6,
1796 SMC_RET1(handle, status);
1801 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3,
1804 SMC_RET1(handle, status);
1809 status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6,
1811 SMC_RET1(handle, status);
1820 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
1823 SMC_RET1(handle, status);
1828 status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5,
1830 SMC_RET1(handle, status);
1835 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1,
1838 SMC_RET1(handle, status);
1843 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4,
1845 SMC_RET1(handle, status);
1855 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
1859 SMC_RET1(handle, status);
1864 status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6,
1866 SMC_RET1(handle, status);
1871 status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3,
1873 SMC_RET1(handle, status);
1878 status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6,
1880 SMC_RET1(handle, status);
1890 status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3,
1893 SMC_RET1(handle, status);
1902 status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
1912 SMC_RET1(handle, status);
1917 status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6,
1919 SMC_RET1(handle, status);
1948 int status = INTEL_SIP_SMC_STATUS_OK;
1959 status = intel_mailbox_fpga_config_isdone(&err_states);
1960 SMC_RET4(handle, status, err_states, 0, 0);
1969 status = intel_fpga_config_start(x1);
1970 SMC_RET4(handle, status, 0, 0, 0);
1973 status = intel_fpga_config_write(x1, x2);
1974 SMC_RET4(handle, status, 0, 0, 0);
1977 status = intel_fpga_config_completed_write(completed_addr,
1996 SMC_RET4(handle, status, 0, 0, 0);
2004 status = intel_secure_reg_read(x1, &retval);
2005 SMC_RET3(handle, status, retval, x1);
2008 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval);
2009 SMC_RET3(handle, status, retval, x1);
2012 status = intel_secure_reg_update(x1, (uint32_t)x2,
2014 SMC_RET3(handle, status, retval, x1);
2017 status = intel_rsu_status(rsu_respbuf,
2019 if (status) {
2020 SMC_RET1(handle, status);
2027 status = intel_rsu_update(x1);
2028 SMC_RET1(handle, status);
2031 status = intel_rsu_notify(x1);
2032 SMC_RET1(handle, status);
2035 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf,
2037 if (status) {
2038 SMC_RET1(handle, status);
2040 SMC_RET2(handle, status, retval);
2049 status = intel_rsu_copy_dcmf_version(x1, x2);
2050 SMC_RET1(handle, status);
2053 status = intel_rsu_get_device_info((uint32_t *)rsu_respbuf,
2055 if (status) {
2056 SMC_RET1(handle, status);
2058 SMC_RET5(handle, status, rsu_respbuf[0], rsu_respbuf[1],
2070 status = intel_rsu_copy_dcmf_status(x1);
2071 SMC_RET1(handle, status);
2081 status = intel_ecc_dbe_notification(x1);
2082 SMC_RET1(handle, status);
2085 status = intel_smc_service_completed(x1, x2, x3, &rcv_id,
2087 SMC_RET4(handle, status, mbox_error, x1, len_in_resp);
2090 status = intel_smc_fw_version(&retval);
2091 SMC_RET2(handle, status, retval);
2096 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6,
2098 SMC_RET3(handle, status, mbox_status, len_in_resp);
2101 status = intel_smc_get_usercode(&retval);
2102 SMC_RET2(handle, status, retval);
2108 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id);
2110 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id);
2112 status = INTEL_SIP_SMC_STATUS_REJECTED;
2115 SMC_RET3(handle, status, x4, x5);
2123 status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
2126 status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
2129 status = INTEL_SIP_SMC_STATUS_REJECTED;
2132 SMC_RET4(handle, status, mbox_error, x6, x7);
2135 status = intel_fcs_random_number_gen(x1, &retval64,
2137 SMC_RET4(handle, status, mbox_error, x1, retval64);
2140 status = intel_fcs_random_number_gen_ext(x1, x2, x3,
2142 SMC_RET1(handle, status);
2145 status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id);
2146 SMC_RET1(handle, status);
2149 status = intel_fcs_get_provision_data(&send_id);
2150 SMC_RET1(handle, status);
2153 status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3,
2155 SMC_RET2(handle, status, mbox_error);
2158 status = intel_hps_set_bridges(x1, x2);
2159 SMC_RET1(handle, status);
2162 status = intel_hwmon_readtemp(x1, &retval);
2163 SMC_RET2(handle, status, retval);
2166 status = intel_hwmon_readvolt(x1, &retval);
2167 SMC_RET2(handle, status, retval);
2170 status = intel_fcs_sigma_teardown(x1, &mbox_error);
2171 SMC_RET2(handle, status, mbox_error);
2174 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error);
2175 SMC_RET4(handle, status, mbox_error, retval, retval2);
2178 status = intel_fcs_attestation_subkey(x1, x2, x3,
2180 SMC_RET4(handle, status, mbox_error, x3, x4);
2183 status = intel_fcs_get_measurement(x1, x2, x3,
2185 SMC_RET4(handle, status, mbox_error, x3, x4);
2188 status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2,
2190 SMC_RET4(handle, status, mbox_error, x2, x3);
2193 status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error);
2194 SMC_RET2(handle, status, mbox_error);
2197 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error);
2198 SMC_RET3(handle, status, mbox_error, retval);
2201 status = intel_fcs_close_crypto_service_session(x1, &mbox_error);
2202 SMC_RET2(handle, status, mbox_error);
2205 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id);
2206 SMC_RET1(handle, status);
2209 status = intel_fcs_export_crypto_service_key(x1, x2, x3,
2211 SMC_RET4(handle, status, mbox_error, x3, x4);
2214 status = intel_fcs_remove_crypto_service_key(x1, x2,
2216 SMC_RET2(handle, status, mbox_error);
2219 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3,
2221 SMC_RET4(handle, status, mbox_error, x3, x4);
2225 status = intel_fcs_get_digest_init(x1, x2, x3,
2227 SMC_RET2(handle, status, mbox_error);
2232 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
2235 SMC_RET4(handle, status, mbox_error, x5, x6);
2240 status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
2243 SMC_RET4(handle, status, mbox_error, x5, x6);
2248 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2251 SMC_RET4(handle, status, mbox_error, x5, x6);
2256 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3,
2259 SMC_RET4(handle, status, mbox_error, x5, x6);
2263 status = intel_fcs_mac_verify_init(x1, x2, x3,
2265 SMC_RET2(handle, status, mbox_error);
2271 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
2274 SMC_RET4(handle, status, mbox_error, x5, x6);
2280 status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
2283 SMC_RET4(handle, status, mbox_error, x5, x6);
2289 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2292 SMC_RET4(handle, status, mbox_error, x5, x6);
2298 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3,
2301 SMC_RET4(handle, status, mbox_error, x5, x6);
2305 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3,
2307 SMC_RET2(handle, status, mbox_error);
2312 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
2315 SMC_RET4(handle, status, mbox_error, x5, x6);
2320 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
2323 SMC_RET4(handle, status, mbox_error, x5, x6);
2328 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
2331 SMC_RET4(handle, status, mbox_error, x5, x6);
2336 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1,
2339 SMC_RET4(handle, status, mbox_error, x5, x6);
2343 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3,
2345 SMC_RET2(handle, status, mbox_error);
2350 status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2,
2353 SMC_RET4(handle, status, mbox_error, x5, x6);
2357 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3,
2359 SMC_RET2(handle, status, mbox_error);
2364 status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1,
2367 SMC_RET4(handle, status, mbox_error, x5, x6);
2371 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3,
2373 SMC_RET2(handle, status, mbox_error);
2379 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
2383 SMC_RET4(handle, status, mbox_error, x5, x6);
2389 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
2392 SMC_RET4(handle, status, mbox_error, x5, x6);
2398 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(
2401 SMC_RET4(handle, status, mbox_error, x5, x6);
2407 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
2411 SMC_RET4(handle, status, mbox_error, x5, x6);
2415 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3,
2417 SMC_RET2(handle, status, mbox_error);
2420 status = intel_fcs_ecdsa_get_pubkey_finalize(
2423 SMC_RET4(handle, status, mbox_error, x3, x4);
2427 status = intel_fcs_ecdh_request_init(x1, x2, x3,
2429 SMC_RET2(handle, status, mbox_error);
2434 status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3,
2436 SMC_RET4(handle, status, mbox_error, x5, x6);
2440 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5,
2442 SMC_RET2(handle, status, mbox_error);
2447 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
2449 SMC_RET1(handle, status);
2454 status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
2456 SMC_RET1(handle, status);
2460 status = intel_smmu_hps_remapper_config(x1);
2461 SMC_RET1(handle, status);
2465 status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
2467 SMC_RET4(handle, status, mbox_error, x1, retval64);
2475 status = intel_sdm_seu_err_read(seu_respbuf,
2477 if (status) {
2478 SMC_RET1(handle, status);
2484 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2);
2485 SMC_RET1(handle, status);