345 int ddr_config_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)  in ddr_config_scrubber()  argument
351 	mmio_write_32(0, umctl2_base + DDR4_PWRCTL_OFFSET);  in ddr_config_scrubber()
354 	temp[0] = mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET);  in ddr_config_scrubber()
355 	temp[1] = mmio_read_32(umctl2_base + DDR4_SBRWDATA0_OFFSET);  in ddr_config_scrubber()
356 	temp[2] = mmio_read_32(umctl2_base + DDR4_SBRSTART0_OFFSET);  in ddr_config_scrubber()
358 		temp[3] = mmio_read_32(umctl2_base + DDR4_SBRWDATA1_OFFSET);  in ddr_config_scrubber()
359 		temp[4] = mmio_read_32(umctl2_base + DDR4_SBRSTART1_OFFSET);  in ddr_config_scrubber()
361 	temp[5] = mmio_read_32(umctl2_base + DDR4_SBRRANGE0_OFFSET);  in ddr_config_scrubber()
362 	temp[6] = mmio_read_32(umctl2_base + DDR4_SBRRANGE1_OFFSET);  in ddr_config_scrubber()
363 	temp[7] = mmio_read_32(umctl2_base + DDR4_ECCCFG0_OFFSET);  in ddr_config_scrubber()
364 	temp[8] = mmio_read_32(umctl2_base + DDR4_ECCCFG1_OFFSET);  in ddr_config_scrubber()
368 		mmio_setbits_32(umctl2_base + DDR4_ECCCFG1_OFFSET,  in ddr_config_scrubber()
372 	mmio_clrbits_32(umctl2_base + DDR4_PCTRL0_OFFSET, DDR4_PCTRL0_PORT_EN);  in ddr_config_scrubber()
374 	mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);  in ddr_config_scrubber()
376 	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),  in ddr_config_scrubber()
394 		       umctl2_base + DDR4_ECCCFG0_OFFSET);  in ddr_config_scrubber()
399 	       umctl2_base + DDR4_SBRCTL_OFFSET);  in ddr_config_scrubber()
402 	ret = ddr_zerofill_scrubber(umctl2_base, umctl2_type);  in ddr_config_scrubber()
408 	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),  in ddr_config_scrubber()
417 	mmio_clrbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);  in ddr_config_scrubber()
420 	mmio_write_32(temp[0], umctl2_base + DDR4_SBRCTL_OFFSET);  in ddr_config_scrubber()
421 	mmio_write_32(temp[1], umctl2_base + DDR4_SBRWDATA0_OFFSET);  in ddr_config_scrubber()
422 	mmio_write_32(temp[2], umctl2_base + DDR4_SBRSTART0_OFFSET);  in ddr_config_scrubber()
424 		mmio_write_32(temp[3], umctl2_base + DDR4_SBRWDATA1_OFFSET);  in ddr_config_scrubber()
425 		mmio_write_32(temp[4], umctl2_base + DDR4_SBRSTART1_OFFSET);  in ddr_config_scrubber()
427 	mmio_write_32(temp[5], umctl2_base + DDR4_SBRRANGE0_OFFSET);  in ddr_config_scrubber()
428 	mmio_write_32(temp[6], umctl2_base + DDR4_SBRRANGE1_OFFSET);  in ddr_config_scrubber()
429 	mmio_write_32(temp[7], umctl2_base + DDR4_ECCCFG0_OFFSET);  in ddr_config_scrubber()
430 	mmio_write_32(temp[8], umctl2_base + DDR4_ECCCFG1_OFFSET);  in ddr_config_scrubber()
433 	if (!(mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET) & DDR4_SBRCTL_SCRUB_WRITE)) {  in ddr_config_scrubber()
435 		mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);  in ddr_config_scrubber()
441 int ddr_zerofill_scrubber(phys_addr_t umctl2_base, enum ddr_type umctl2_type)  in ddr_zerofill_scrubber()  argument
446 	mmio_write_32(0, umctl2_base + DDR4_SBRWDATA0_OFFSET);  in ddr_zerofill_scrubber()
447 	mmio_write_32(0, umctl2_base + DDR4_SBRSTART0_OFFSET);  in ddr_zerofill_scrubber()
449 		mmio_write_32(0, umctl2_base + DDR4_SBRWDATA1_OFFSET);  in ddr_zerofill_scrubber()
450 		mmio_write_32(0, umctl2_base + DDR4_SBRSTART1_OFFSET);  in ddr_zerofill_scrubber()
452 	mmio_write_32(0, umctl2_base + DDR4_SBRRANGE0_OFFSET);  in ddr_zerofill_scrubber()
453 	mmio_write_32(0, umctl2_base + DDR4_SBRRANGE1_OFFSET);  in ddr_zerofill_scrubber()
458 	mmio_setbits_32(umctl2_base + DDR4_SBRCTL_OFFSET, DDR4_SBRCTL_SCRUB_EN);  in ddr_zerofill_scrubber()
460 	ret = poll_idle_status((umctl2_base + DDR4_SBRSTAT_OFFSET),  in ddr_zerofill_scrubber()