347 	uint32_t temp[9] = {0};  in ddr_config_scrubber()  local
354 	temp[0] = mmio_read_32(umctl2_base + DDR4_SBRCTL_OFFSET);  in ddr_config_scrubber()
355 	temp[1] = mmio_read_32(umctl2_base + DDR4_SBRWDATA0_OFFSET);  in ddr_config_scrubber()
356 	temp[2] = mmio_read_32(umctl2_base + DDR4_SBRSTART0_OFFSET);  in ddr_config_scrubber()
358 		temp[3] = mmio_read_32(umctl2_base + DDR4_SBRWDATA1_OFFSET);  in ddr_config_scrubber()
359 		temp[4] = mmio_read_32(umctl2_base + DDR4_SBRSTART1_OFFSET);  in ddr_config_scrubber()
361 	temp[5] = mmio_read_32(umctl2_base + DDR4_SBRRANGE0_OFFSET);  in ddr_config_scrubber()
362 	temp[6] = mmio_read_32(umctl2_base + DDR4_SBRRANGE1_OFFSET);  in ddr_config_scrubber()
363 	temp[7] = mmio_read_32(umctl2_base + DDR4_ECCCFG0_OFFSET);  in ddr_config_scrubber()
364 	temp[8] = mmio_read_32(umctl2_base + DDR4_ECCCFG1_OFFSET);  in ddr_config_scrubber()
420 	mmio_write_32(temp[0], umctl2_base + DDR4_SBRCTL_OFFSET);  in ddr_config_scrubber()
421 	mmio_write_32(temp[1], umctl2_base + DDR4_SBRWDATA0_OFFSET);  in ddr_config_scrubber()
422 	mmio_write_32(temp[2], umctl2_base + DDR4_SBRSTART0_OFFSET);  in ddr_config_scrubber()
424 		mmio_write_32(temp[3], umctl2_base + DDR4_SBRWDATA1_OFFSET);  in ddr_config_scrubber()
425 		mmio_write_32(temp[4], umctl2_base + DDR4_SBRSTART1_OFFSET);  in ddr_config_scrubber()
427 	mmio_write_32(temp[5], umctl2_base + DDR4_SBRRANGE0_OFFSET);  in ddr_config_scrubber()
428 	mmio_write_32(temp[6], umctl2_base + DDR4_SBRRANGE1_OFFSET);  in ddr_config_scrubber()
429 	mmio_write_32(temp[7], umctl2_base + DDR4_ECCCFG0_OFFSET);  in ddr_config_scrubber()
430 	mmio_write_32(temp[8], umctl2_base + DDR4_ECCCFG1_OFFSET);  in ddr_config_scrubber()