Lines Matching refs:IMX_SIM1_BASE
37 #define RVBARADDRx(c) (IMX_SIM1_BASE + 0x5c + 0x4 * (c))
38 #define WKPUx(c) (IMX_SIM1_BASE + 0x3c + 0x4 * (c))
83 mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) | BIT_32(24 + cpu)); in imx_pwr_set_cpu_entry()
85 while (!(mmio_read_32(IMX_SIM1_BASE + 0x8) & BIT_32(26 + cpu))) { in imx_pwr_set_cpu_entry()
89 mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) & ~BIT_32(24 + cpu)); in imx_pwr_set_cpu_entry()
91 mmio_write_32(IMX_SIM1_BASE + 0x8, mmio_read_32(IMX_SIM1_BASE + 0x8) | BIT_32(26 + cpu)); in imx_pwr_set_cpu_entry()
111 mmio_write_32(IMX_SIM1_BASE + 0x3c + 0x4 * cpu, 0xffffffff); in imx_pwr_domain_on()
312 mmio_write_32(IMX_SIM1_BASE + 0x3c + 0x4 * cpu, 0x7fffffe3); in imx_domain_suspend()
316 mmio_write_32(IMX_SIM1_BASE + 0x3c + 0x4 * cpu, 0x7fffffe3); in imx_domain_suspend()
422 mmio_write_32(IMX_SIM1_BASE + 0x3c + 0x4 * cpu, 0x0); in imx_domain_suspend_finish()
554 mmio_write_32(IMX_SIM1_BASE + 0x3c, 0xffffffff); in plat_setup_psci_ops()