Lines Matching refs:IMX_LPAV_SIM_BASE
34 #define IMX_LPAV_SIM_BASE 0x2DA50000 macro
304 mmio_clrbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL, LPDDR_AUTO_LP_MODE_DISABLE); in dram_enter_self_refresh()
305 mmio_clrsetbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL, in dram_enter_self_refresh()
308 mmio_setbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL2, LPDDR_EN_CLKGATE); in dram_enter_self_refresh()
310 mmio_clrbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL2, LPDDR_MAX_CLKDIV_EN); in dram_enter_self_refresh()
343 mmio_clrbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL, LPDDR_AUTO_LP_MODE_DISABLE); in dram_enter_retention()
344 mmio_clrsetbits_32(IMX_LPAV_SIM_BASE + LPDDR_CTRL, in dram_enter_retention()
616 #define AVD_SIM_LPDDR_CTRL (IMX_LPAV_SIM_BASE + 0x14)
617 #define AVD_SIM_LPDDR_CTRL2 (IMX_LPAV_SIM_BASE + 0x18)
670 mmio_write_32(IMX_LPAV_SIM_BASE, 0x1); in lpddr4_dfs()
675 mmio_write_32(IMX_LPAV_SIM_BASE, 0x0); in lpddr4_dfs()