Lines Matching refs:DGO_CTRL1
610 #define DGO_CTRL1 U(0xc) macro
622 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
623 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { in usb_wakeup_enable()
627 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
628 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); in usb_wakeup_enable()
635 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
636 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { in usb_wakeup_enable()
640 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
641 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); in usb_wakeup_enable()
649 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
650 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { in usb_wakeup_enable()
654 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); in usb_wakeup_enable()
655 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); in usb_wakeup_enable()