48 #define PAXB_OFFSET(core)                (PAXB_BASE + \  macro
334 	uint32_t clk_ctrl = PAXB_OFFSET(core_idx) + PAXB_CLK_CTRL_OFFSET;  in paxb_perst_ctrl()
363 			val = mmio_read_32(PAXB_OFFSET(core_idx) +  in paxb_start_link_up()
522 	mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_ADDR_OFFSET,  in paxb_rc_cfg_write()
525 	mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET, val);  in paxb_rc_cfg_write()
532 	mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_ADDR_OFFSET,  in paxb_rc_cfg_read()
535 	val = mmio_read_32(PAXB_OFFSET(core_idx) + PAXB_CFG_IND_DATA_OFFSET);  in paxb_rc_cfg_read()
711 		mmio_write_32(PAXB_OFFSET(i) + PAXB_0_DEFAULT_IMAP,  in paxb_ib_regs_bypass()
713 		mmio_write_32(PAXB_OFFSET(i) + PAXB_0_DEFAULT_IMAP_AXUSER,  in paxb_ib_regs_bypass()
715 		mmio_write_32(PAXB_OFFSET(i) + PAXB_0_DEFAULT_IMAP_AXCACHE,  in paxb_ib_regs_bypass()
719 		mmio_setbits_32(PAXB_OFFSET(i) +  in paxb_ib_regs_bypass()
722 		mmio_write_32(PAXB_OFFSET(i) + PAXB_IARR0_BASE_OFFSET,  in paxb_ib_regs_bypass()
725 			mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP0_OFFSET(j),  in paxb_ib_regs_bypass()
742 		mmio_write_32(PAXB_OFFSET(core_idx) + PAXB_IARR2_LOWER_OFFSET,  in paxb_ib_regs_init()
744 		mmio_setbits_32(PAXB_OFFSET(core_idx) +  in paxb_ib_regs_init()
759 		mmio_write_32(PAXB_OFFSET(core_idx) +  in paxb_cfg_apb_timeout()
796 		mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP2_OFFSET,  in paxb_cfg_coherency()
800 		mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP0_0_AXUSER_OFFSET,  in paxb_cfg_coherency()
803 		mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP2_AXUSER_OFFSET,  in paxb_cfg_coherency()
808 			mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP3_OFFSET(j),  in paxb_cfg_coherency()
810 			mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP4_OFFSET(j),  in paxb_cfg_coherency()
814 			mmio_write_32(PAXB_OFFSET(i) + PAXB_IMAP0_OFFSET(j),  in paxb_cfg_coherency()
817 			mmio_write_32(PAXB_OFFSET(i) +  in paxb_cfg_coherency()
820 			mmio_write_32(PAXB_OFFSET(i) +  in paxb_cfg_coherency()