Lines Matching refs:pte
337 uint64_t addr, *pte, *l0_base, *l1_base; in smmu_set_pgtbl() local
362 pte = l0_base + l0_index; in smmu_set_pgtbl()
363 if (*pte == 0x0) { in smmu_set_pgtbl()
364 *pte |= ((uint64_t)l1_base & ARM_LPAE_PTE_TABLE_MASK); in smmu_set_pgtbl()
366 *pte |= ARM_LPAE_PTE_NSTABLE; in smmu_set_pgtbl()
367 *pte |= ARM_LPAE_PTE_TABLE; in smmu_set_pgtbl()
368 *pte |= ARM_LPAE_PTE_VALID; in smmu_set_pgtbl()
374 pte = l1_base + l1_index; in smmu_set_pgtbl()
377 *pte = 0x0; in smmu_set_pgtbl()
378 *pte |= (addr & ARM_LPAE_PTE_L1_ADDR_MASK); in smmu_set_pgtbl()
380 *pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV << in smmu_set_pgtbl()
383 *pte |= (1 << ARM_LPAE_PTE_NS); in smmu_set_pgtbl()
385 *pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE << in smmu_set_pgtbl()
387 *pte |= (1 << ARM_LPAE_PTE_NS); in smmu_set_pgtbl()
389 *pte |= (ARM_LPAE_PTE_AP_EL0_RW << ARM_LPAE_PTE_AP); in smmu_set_pgtbl()
390 *pte |= (ARM_LPAE_PTE_SH_INNER << ARM_LPAE_PTE_SH); in smmu_set_pgtbl()
391 *pte |= (1 << ARM_LPAE_PTE_AF); in smmu_set_pgtbl()
392 *pte |= ARM_LPAE_PTE_VALID; in smmu_set_pgtbl()