158 static int write_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t data)  in write_swreg_config()  argument
163 	cmd = BSTI_CMD(0x1, BSTI_WRITE, reg_id, addr, BSTI_COMMAND_TA, data);  in write_swreg_config()
169 			sw_reg_name[reg_id-1], addr);  in write_swreg_config()
175 static int read_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t *data)  in read_swreg_config()  argument
180 	cmd = BSTI_CMD(0x1, BSTI_READ, reg_id, addr, BSTI_COMMAND_TA, PHY_REG0);  in read_swreg_config()
186 			sw_reg_name[reg_id-1], addr);  in read_swreg_config()
195 static int swreg_config_done(enum sw_reg reg_id)  in swreg_config_done()  argument
200 	ret = read_swreg_config(reg_id, PHY_REG0, &read_data);  in swreg_config_done()
206 	ret = write_swreg_config(reg_id, PHY_REG0, read_data);  in swreg_config_done()
210 	ret = read_swreg_config(reg_id, PHY_REG0, &read_data);  in swreg_config_done()
215 	ret = write_swreg_config(reg_id, PHY_REG0, read_data);  in swreg_config_done()
225 	enum sw_reg reg_id;  in dump_swreg_firmware()  local
230 	for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) {  in dump_swreg_firmware()
231 		INFO("SWREG: %s\n", sw_reg_name[reg_id - 1]);  in dump_swreg_firmware()
233 			ret = read_swreg_config(reg_id, addr, &data);  in dump_swreg_firmware()
242 int set_swreg(enum sw_reg reg_id, uint32_t micro_volts)  in set_swreg()  argument
254 	ret = read_swreg_config(reg_id, PHY_REGC, &programmed_step);  in set_swreg()
258 	if (reg_id == DDR_VDDC)  in set_swreg()
264 		ret = write_swreg_config(reg_id, PHY_REGC, step);  in set_swreg()
268 		if (reg_id == DDR_VDDC)  in set_swreg()
271 		ret = write_swreg_config(reg_id, PHY_REG0,  in set_swreg()
276 		ret = write_swreg_config(reg_id, PHY_REG0,  in set_swreg()
282 	INFO("%s voltage updated to %duV\n", sw_reg_name[reg_id-1],  in set_swreg()
292 	ERROR("Failed to set %s voltage to %duV\n", sw_reg_name[reg_id-1],  in set_swreg()
302 	enum sw_reg reg_id;  in swreg_firmware_update()  local
308 	for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) {  in swreg_firmware_update()
311 			ret = write_swreg_config(reg_id, addr,  in swreg_firmware_update()
312 						 FM_DATA[reg_id - 1][addr]);  in swreg_firmware_update()
319 	for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) {  in swreg_firmware_update()
324 		if ((reg_id == DDRIO_SLAVE) || (reg_id == VDDC1))  in swreg_firmware_update()
327 		ret = swreg_config_done(reg_id);  in swreg_firmware_update()
330 				, sw_reg_name[reg_id-1]);  in swreg_firmware_update()
335 	for (reg_id = DDR_VDDC; reg_id <= DDRIO_MASTER; reg_id++) {  in swreg_firmware_update()
341 		if (reg_id == IHOST_ARRAY)  in swreg_firmware_update()
345 			ret = read_swreg_config(reg_id, addr, &data);  in swreg_firmware_update()
347 				(data != FM_DATA[reg_id - 1][addr]))) {  in swreg_firmware_update()
349 					sw_reg_name[reg_id - 1], addr);  in swreg_firmware_update()
351 					data, FM_DATA[reg_id - 1][addr]);  in swreg_firmware_update()
371 		sw_reg_name[reg_id-1]);  in swreg_firmware_update()