Lines Matching refs:r0
24 TLB_INVALIDATE(r0, TLBIALL)
26 mov r3, r0
27 ldr r0, =mmu_cfg_params
30 ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
34 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
38 ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
39 ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]
81 TLB_INVALIDATE(r0, TLBIALL)
83 mov r3, r0
84 ldr r0, =mmu_cfg_params
87 ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
91 ldr r2, [r0, #(MMU_CFG_TCR << 3)]
95 ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
96 ldr r2, [r0, #((MMU_CFG_TTBR0 << 3) + 4)]