Lines Matching refs:CLKSRC
46 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ macro
138 #define CLK_MPU_HSI CLKSRC(MUX_MPU, 0)
139 #define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
140 #define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2)
141 #define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
143 #define CLK_AXI_HSI CLKSRC(MUX_AXI, 0)
144 #define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
145 #define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2)
147 #define CLK_MCU_HSI CLKSRC(MUX_MCU, 0)
148 #define CLK_MCU_HSE CLKSRC(MUX_MCU, 1)
149 #define CLK_MCU_CSI CLKSRC(MUX_MCU, 2)
150 #define CLK_MCU_PLL3P CLKSRC(MUX_MCU, 3)
152 #define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0)
153 #define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
155 #define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
156 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
157 #define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
159 #define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0)
160 #define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
161 #define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2)
162 #define CLK_PLL4_I2SCKIN CLKSRC(MUX_PLL4, 3)
201 #define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0)
202 #define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
203 #define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2)
204 #define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
205 #define CLK_I2C12_DISABLED CLKSRC(MUX_I2C12, 7)
207 #define CLK_I2C35_PCLK1 CLKSRC(MUX_I2C35, 0)
208 #define CLK_I2C35_PLL4R CLKSRC(MUX_I2C35, 1)
209 #define CLK_I2C35_HSI CLKSRC(MUX_I2C35, 2)
210 #define CLK_I2C35_CSI CLKSRC(MUX_I2C35, 3)
211 #define CLK_I2C35_DISABLED CLKSRC(MUX_I2C35, 7)
213 #define CLK_I2C46_PCLK5 CLKSRC(MUX_I2C46, 0)
214 #define CLK_I2C46_PLL3Q CLKSRC(MUX_I2C46, 1)
215 #define CLK_I2C46_HSI CLKSRC(MUX_I2C46, 2)
216 #define CLK_I2C46_CSI CLKSRC(MUX_I2C46, 3)
217 #define CLK_I2C46_DISABLED CLKSRC(MUX_I2C46, 7)
219 #define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0)
220 #define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
221 #define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2)
222 #define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
223 #define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
224 #define CLK_SAI1_DISABLED CLKSRC(MUX_SAI1, 7)
226 #define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0)
227 #define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
228 #define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2)
229 #define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
230 #define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)
231 #define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5)
232 #define CLK_SAI2_DISABLED CLKSRC(MUX_SAI2, 7)
234 #define CLK_SAI3_PLL4Q CLKSRC(MUX_SAI3, 0)
235 #define CLK_SAI3_PLL3Q CLKSRC(MUX_SAI3, 1)
236 #define CLK_SAI3_I2SCKIN CLKSRC(MUX_SAI3, 2)
237 #define CLK_SAI3_CKPER CLKSRC(MUX_SAI3, 3)
238 #define CLK_SAI3_PLL3R CLKSRC(MUX_SAI3, 4)
239 #define CLK_SAI3_DISABLED CLKSRC(MUX_SAI3, 7)
241 #define CLK_SAI4_PLL4Q CLKSRC(MUX_SAI4, 0)
242 #define CLK_SAI4_PLL3Q CLKSRC(MUX_SAI4, 1)
243 #define CLK_SAI4_I2SCKIN CLKSRC(MUX_SAI4, 2)
244 #define CLK_SAI4_CKPER CLKSRC(MUX_SAI4, 3)
245 #define CLK_SAI4_PLL3R CLKSRC(MUX_SAI4, 4)
246 #define CLK_SAI4_DISABLED CLKSRC(MUX_SAI4, 7)
248 #define CLK_SPI2S1_PLL4P CLKSRC(MUX_SPI2S1, 0)
249 #define CLK_SPI2S1_PLL3Q CLKSRC(MUX_SPI2S1, 1)
250 #define CLK_SPI2S1_I2SCKIN CLKSRC(MUX_SPI2S1, 2)
251 #define CLK_SPI2S1_CKPER CLKSRC(MUX_SPI2S1, 3)
252 #define CLK_SPI2S1_PLL3R CLKSRC(MUX_SPI2S1, 4)
253 #define CLK_SPI2S1_DISABLED CLKSRC(MUX_SPI2S1, 7)
255 #define CLK_SPI2S23_PLL4P CLKSRC(MUX_SPI2S23, 0)
256 #define CLK_SPI2S23_PLL3Q CLKSRC(MUX_SPI2S23, 1)
257 #define CLK_SPI2S23_I2SCKIN CLKSRC(MUX_SPI2S23, 2)
258 #define CLK_SPI2S23_CKPER CLKSRC(MUX_SPI2S23, 3)
259 #define CLK_SPI2S23_PLL3R CLKSRC(MUX_SPI2S23, 4)
260 #define CLK_SPI2S23_DISABLED CLKSRC(MUX_SPI2S23, 7)
262 #define CLK_SPI45_PCLK2 CLKSRC(MUX_SPI45, 0)
263 #define CLK_SPI45_PLL4Q CLKSRC(MUX_SPI45, 1)
264 #define CLK_SPI45_HSI CLKSRC(MUX_SPI45, 2)
265 #define CLK_SPI45_CSI CLKSRC(MUX_SPI45, 3)
266 #define CLK_SPI45_HSE CLKSRC(MUX_SPI45, 4)
267 #define CLK_SPI45_DISABLED CLKSRC(MUX_SPI45, 7)
269 #define CLK_SPI6_PCLK5 CLKSRC(MUX_SPI6, 0)
270 #define CLK_SPI6_PLL4Q CLKSRC(MUX_SPI6, 1)
271 #define CLK_SPI6_HSI CLKSRC(MUX_SPI6, 2)
272 #define CLK_SPI6_CSI CLKSRC(MUX_SPI6, 3)
273 #define CLK_SPI6_HSE CLKSRC(MUX_SPI6, 4)
274 #define CLK_SPI6_PLL3Q CLKSRC(MUX_SPI6, 5)
275 #define CLK_SPI6_DISABLED CLKSRC(MUX_SPI6, 7)
277 #define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0)
278 #define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
279 #define CLK_UART6_HSI CLKSRC(MUX_UART6, 2)
280 #define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
281 #define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
282 #define CLK_UART6_DISABLED CLKSRC(MUX_UART6, 7)
284 #define CLK_UART24_PCLK1 CLKSRC(MUX_UART24, 0)
285 #define CLK_UART24_PLL4Q CLKSRC(MUX_UART24, 1)
286 #define CLK_UART24_HSI CLKSRC(MUX_UART24, 2)
287 #define CLK_UART24_CSI CLKSRC(MUX_UART24, 3)
288 #define CLK_UART24_HSE CLKSRC(MUX_UART24, 4)
289 #define CLK_UART24_DISABLED CLKSRC(MUX_UART24, 7)
291 #define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0)
292 #define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
293 #define CLK_UART35_HSI CLKSRC(MUX_UART35, 2)
294 #define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
295 #define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
296 #define CLK_UART35_DISABLED CLKSRC(MUX_UART35, 7)
298 #define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0)
299 #define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
300 #define CLK_UART78_HSI CLKSRC(MUX_UART78, 2)
301 #define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
302 #define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
303 #define CLK_UART78_DISABLED CLKSRC(MUX_UART78, 7)
305 #define CLK_UART1_PCLK5 CLKSRC(MUX_UART1, 0)
306 #define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
307 #define CLK_UART1_HSI CLKSRC(MUX_UART1, 2)
308 #define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
309 #define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
310 #define CLK_UART1_HSE CLKSRC(MUX_UART1, 5)
311 #define CLK_UART1_DISABLED CLKSRC(MUX_UART1, 7)
313 #define CLK_SDMMC12_HCLK6 CLKSRC(MUX_SDMMC12, 0)
314 #define CLK_SDMMC12_PLL3R CLKSRC(MUX_SDMMC12, 1)
315 #define CLK_SDMMC12_PLL4P CLKSRC(MUX_SDMMC12, 2)
316 #define CLK_SDMMC12_HSI CLKSRC(MUX_SDMMC12, 3)
317 #define CLK_SDMMC12_DISABLED CLKSRC(MUX_SDMMC12, 7)
319 #define CLK_SDMMC3_HCLK2 CLKSRC(MUX_SDMMC3, 0)
320 #define CLK_SDMMC3_PLL3R CLKSRC(MUX_SDMMC3, 1)
321 #define CLK_SDMMC3_PLL4P CLKSRC(MUX_SDMMC3, 2)
322 #define CLK_SDMMC3_HSI CLKSRC(MUX_SDMMC3, 3)
323 #define CLK_SDMMC3_DISABLED CLKSRC(MUX_SDMMC3, 7)
325 #define CLK_ETH_PLL4P CLKSRC(MUX_ETH, 0)
326 #define CLK_ETH_PLL3Q CLKSRC(MUX_ETH, 1)
327 #define CLK_ETH_DISABLED CLKSRC(MUX_ETH, 3)
329 #define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0)
330 #define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
331 #define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2)
332 #define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
334 #define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0)
335 #define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
336 #define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2)
337 #define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
339 #define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0)
340 #define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
341 #define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2)
342 #define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
344 #define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0)
345 #define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
346 #define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2)
347 #define CLK_SPDIF_DISABLED CLKSRC(MUX_SPDIF, 3)
349 #define CLK_CEC_LSE CLKSRC(MUX_CEC, 0)
350 #define CLK_CEC_LSI CLKSRC(MUX_CEC, 1)
351 #define CLK_CEC_CSI_DIV122 CLKSRC(MUX_CEC, 2)
352 #define CLK_CEC_DISABLED CLKSRC(MUX_CEC, 3)
354 #define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0)
355 #define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
356 #define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2)
357 #define CLK_USBPHY_DISABLED CLKSRC(MUX_USBPHY, 3)
359 #define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0)
360 #define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
362 #define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0)
363 #define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
364 #define CLK_RNG1_LSE CLKSRC(MUX_RNG1, 2)
365 #define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
367 #define CLK_RNG2_CSI CLKSRC(MUX_RNG2, 0)
368 #define CLK_RNG2_PLL4R CLKSRC(MUX_RNG2, 1)
369 #define CLK_RNG2_LSE CLKSRC(MUX_RNG2, 2)
370 #define CLK_RNG2_LSI CLKSRC(MUX_RNG2, 3)
372 #define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0)
373 #define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
374 #define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2)
375 #define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
377 #define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0)
378 #define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
379 #define CLK_STGEN_DISABLED CLKSRC(MUX_STGEN, 3)
381 #define CLK_DSI_DSIPLL CLKSRC(MUX_DSI, 0)
382 #define CLK_DSI_PLL4P CLKSRC(MUX_DSI, 1)
384 #define CLK_ADC_PLL4R CLKSRC(MUX_ADC, 0)
385 #define CLK_ADC_CKPER CLKSRC(MUX_ADC, 1)
386 #define CLK_ADC_PLL3Q CLKSRC(MUX_ADC, 2)
387 #define CLK_ADC_DISABLED CLKSRC(MUX_ADC, 3)
389 #define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0)
390 #define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
391 #define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2)
392 #define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
393 #define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
394 #define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5)
395 #define CLK_LPTIM45_DISABLED CLKSRC(MUX_LPTIM45, 7)
397 #define CLK_LPTIM23_PCLK3 CLKSRC(MUX_LPTIM23, 0)
398 #define CLK_LPTIM23_PLL4Q CLKSRC(MUX_LPTIM23, 1)
399 #define CLK_LPTIM23_CKPER CLKSRC(MUX_LPTIM23, 2)
400 #define CLK_LPTIM23_LSE CLKSRC(MUX_LPTIM23, 3)
401 #define CLK_LPTIM23_LSI CLKSRC(MUX_LPTIM23, 4)
402 #define CLK_LPTIM23_DISABLED CLKSRC(MUX_LPTIM23, 7)
404 #define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0)
405 #define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
406 #define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2)
407 #define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
408 #define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
409 #define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5)
410 #define CLK_LPTIM1_DISABLED CLKSRC(MUX_LPTIM1, 7)