Lines Matching refs:CLKSRC
72 #define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ macro
141 #define CLK_MPU_HSI CLKSRC(MUX_MPU, 0)
142 #define CLK_MPU_HSE CLKSRC(MUX_MPU, 1)
143 #define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2)
144 #define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
146 #define CLK_AXI_HSI CLKSRC(MUX_AXI, 0)
147 #define CLK_AXI_HSE CLKSRC(MUX_AXI, 1)
148 #define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2)
150 #define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0)
151 #define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1)
152 #define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2)
153 #define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3)
155 #define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0)
156 #define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1)
158 #define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0)
159 #define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1)
160 #define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2)
162 #define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0)
163 #define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1)
164 #define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2)
186 #define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0)
187 #define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1)
188 #define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2)
189 #define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
191 #define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0)
192 #define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1)
193 #define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2)
194 #define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
196 #define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0)
197 #define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1)
198 #define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2)
199 #define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3)
201 #define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0)
202 #define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1)
203 #define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2)
204 #define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3)
206 #define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0)
207 #define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1)
208 #define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2)
209 #define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3)
211 #define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0)
212 #define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1)
213 #define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2)
214 #define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3)
215 #define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4)
217 #define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0)
218 #define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1)
219 #define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2)
220 #define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3)
221 #define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4)
223 #define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0)
224 #define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1)
225 #define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2)
226 #define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3)
227 #define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4)
228 #define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5)
230 #define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0)
231 #define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1)
232 #define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2)
233 #define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3)
234 #define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4)
236 #define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0)
237 #define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1)
238 #define CLK_UART1_HSI CLKSRC(MUX_UART1, 2)
239 #define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
240 #define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
241 #define CLK_UART1_HSE CLKSRC(MUX_UART1, 5)
243 #define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0)
244 #define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1)
245 #define CLK_UART2_HSI CLKSRC(MUX_UART2, 2)
246 #define CLK_UART2_CSI CLKSRC(MUX_UART2, 3)
247 #define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4)
248 #define CLK_UART2_HSE CLKSRC(MUX_UART2, 5)
250 #define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0)
251 #define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1)
252 #define CLK_UART35_HSI CLKSRC(MUX_UART35, 2)
253 #define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
254 #define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
256 #define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0)
257 #define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1)
258 #define CLK_UART4_HSI CLKSRC(MUX_UART4, 2)
259 #define CLK_UART4_CSI CLKSRC(MUX_UART4, 3)
260 #define CLK_UART4_HSE CLKSRC(MUX_UART4, 4)
262 #define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0)
263 #define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1)
264 #define CLK_UART6_HSI CLKSRC(MUX_UART6, 2)
265 #define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
266 #define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
268 #define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0)
269 #define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1)
270 #define CLK_UART78_HSI CLKSRC(MUX_UART78, 2)
271 #define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
272 #define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
274 #define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0)
275 #define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1)
276 #define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2)
277 #define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
278 #define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
279 #define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5)
281 #define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0)
282 #define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1)
283 #define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2)
284 #define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3)
285 #define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4)
287 #define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0)
288 #define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1)
289 #define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2)
290 #define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3)
291 #define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4)
293 #define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0)
294 #define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1)
295 #define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2)
296 #define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
297 #define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
298 #define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5)
300 #define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0)
301 #define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1)
302 #define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2)
303 #define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
304 #define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
306 #define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0)
307 #define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1)
308 #define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2)
309 #define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
310 #define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)
311 #define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5)
313 #define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0)
314 #define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1)
315 #define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2)
316 #define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
318 #define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0)
319 #define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1)
320 #define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2)
322 #define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0)
323 #define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1)
324 #define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2)
326 #define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0)
327 #define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1)
328 #define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2)
330 #define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0)
331 #define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1)
332 #define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2)
333 #define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3)
335 #define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0)
336 #define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1)
337 #define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2)
338 #define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3)
340 #define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0)
341 #define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1)
343 #define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0)
344 #define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1)
346 #define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0)
347 #define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1)
348 #define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2)
350 #define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0)
351 #define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1)
353 #define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0)
354 #define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1)
355 #define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2)
356 #define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
358 #define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0)
359 #define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1)
360 #define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2)
361 #define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
363 #define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0)
364 #define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1)
366 #define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
368 #define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0)
369 #define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1)
371 #define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0)
372 #define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1)
373 #define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2)
374 #define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3)
376 #define CLK_SAES_AXI CLKSRC(MUX_SAES, 0)
377 #define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1)
378 #define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2)
379 #define CLK_SAES_LSI CLKSRC(MUX_SAES, 3)