20 static uintptr_t get_base_addr(const struct stm32mp_ddr_priv *priv, enum stm32mp_ddr_base_type base)  in get_base_addr()
23 		return (uintptr_t)priv->phy;  in get_base_addr()
25 		return (uintptr_t)priv->ctl;  in get_base_addr()
35 	uintptr_t base_addr = get_base_addr(priv, base);  in stm32mp_ddr_set_reg()
40 		uintptr_t ptr = base_addr + desc[i].offset;  in stm32mp_ddr_set_reg()
52 			value = *((uint32_t *)((uintptr_t)param +  in stm32mp_ddr_set_reg()
67 	mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);  in stm32mp_ddr_start_sw_done()
69 		(uintptr_t)&ctl->swctl,  mmio_read_32((uintptr_t)&ctl->swctl));  in stm32mp_ddr_start_sw_done()
78 	mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);  in stm32mp_ddr_wait_sw_done_ack()
80 		(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));  in stm32mp_ddr_wait_sw_done_ack()
84 		swstat = mmio_read_32((uintptr_t)&ctl->swstat);  in stm32mp_ddr_wait_sw_done_ack()
86 			(uintptr_t)&ctl->swstat, swstat);  in stm32mp_ddr_wait_sw_done_ack()
93 		(uintptr_t)&ctl->swstat, swstat);  in stm32mp_ddr_wait_sw_done_ack()
99 	mmio_setbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);  in stm32mp_ddr_enable_axi_port()
100 	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,  in stm32mp_ddr_enable_axi_port()
101 		mmio_read_32((uintptr_t)&ctl->pctrl_0));  in stm32mp_ddr_enable_axi_port()
105 	mmio_setbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);  in stm32mp_ddr_enable_axi_port()
106 	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,  in stm32mp_ddr_enable_axi_port()
107 		mmio_read_32((uintptr_t)&ctl->pctrl_1));  in stm32mp_ddr_enable_axi_port()
117 	mmio_clrbits_32((uintptr_t)&ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);  in stm32mp_ddr_disable_axi_port()
118 	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,  in stm32mp_ddr_disable_axi_port()
119 		mmio_read_32((uintptr_t)&ctl->pctrl_0));  in stm32mp_ddr_disable_axi_port()
123 	mmio_clrbits_32((uintptr_t)&ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN);  in stm32mp_ddr_disable_axi_port()
124 	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,  in stm32mp_ddr_disable_axi_port()
125 		mmio_read_32((uintptr_t)&ctl->pctrl_1));  in stm32mp_ddr_disable_axi_port()
135 		pstat = mmio_read_32((uintptr_t)&ctl->pstat);  in stm32mp_ddr_disable_axi_port()
137 			(uintptr_t)&ctl->pstat, pstat);  in stm32mp_ddr_disable_axi_port()
148 	return (mmio_read_32((uintptr_t)&ctl->pctrl_0) & DDRCTRL_PCTRL_N_PORT_EN) != 0U;  in ddr_is_axi_port_enabled()
153 	mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);  in stm32mp_ddr_enable_host_interface()
155 		(uintptr_t)&ctl->dbg1,  in stm32mp_ddr_enable_host_interface()
156 		mmio_read_32((uintptr_t)&ctl->dbg1));  in stm32mp_ddr_enable_host_interface()
165 	mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);  in stm32mp_ddr_disable_host_interface()
167 		(uintptr_t)&ctl->dbg1,  in stm32mp_ddr_disable_host_interface()
168 		mmio_read_32((uintptr_t)&ctl->dbg1));  in stm32mp_ddr_disable_host_interface()
182 		dbgcam = mmio_read_32((uintptr_t)&ctl->dbgcam);  in stm32mp_ddr_disable_host_interface()
184 			(uintptr_t)&ctl->dbgcam, dbgcam);  in stm32mp_ddr_disable_host_interface()
195 	return (mmio_read_32((uintptr_t)&ctl->dbg1) & DDRCTRL_DBG1_DIS_HIF) == 0U;  in ddr_is_host_interface_enabled()
205 	mmio_setbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);  in stm32mp_ddr_sw_selfref_entry()
207 		(uintptr_t)&ctl->pwrctl,  in stm32mp_ddr_sw_selfref_entry()
208 		mmio_read_32((uintptr_t)&ctl->pwrctl));  in stm32mp_ddr_sw_selfref_entry()
218 		stat = mmio_read_32((uintptr_t)&ctl->stat);  in stm32mp_ddr_sw_selfref_entry()
233 	mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_SW);  in stm32mp_ddr_sw_selfref_exit()
235 		(uintptr_t)&ctl->pwrctl,  in stm32mp_ddr_sw_selfref_exit()
236 		mmio_read_32((uintptr_t)&ctl->pwrctl));  in stm32mp_ddr_sw_selfref_exit()
278 	rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()
280 		mmio_clrbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);  in stm32mp_ddr_wait_refresh_update_done_ack()
282 		mmio_setbits_32((uintptr_t)&ctl->rfshctl3, refresh_update_level);  in stm32mp_ddr_wait_refresh_update_done_ack()
287 		(uintptr_t)&ctl->rfshctl3, mmio_read_32((uintptr_t)&ctl->rfshctl3));  in stm32mp_ddr_wait_refresh_update_done_ack()
291 		rfshctl3 = mmio_read_32((uintptr_t)&ctl->rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()
292 		VERBOSE("[0x%lx] rfshctl3 = 0x%x ", (uintptr_t)&ctl->rfshctl3, rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()
298 	VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()