38 	VERBOSE("init %s\n", ddr_registers[type].name);  in stm32mp_ddr_set_reg()
68 	VERBOSE("[0x%lx] swctl = 0x%x\n",  in stm32mp_ddr_start_sw_done()
79 	VERBOSE("[0x%lx] swctl = 0x%x\n",  in stm32mp_ddr_wait_sw_done_ack()
85 		VERBOSE("[0x%lx] swstat = 0x%x ",  in stm32mp_ddr_wait_sw_done_ack()
92 	VERBOSE("[0x%lx] swstat = 0x%x\n",  in stm32mp_ddr_wait_sw_done_ack()
100 	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,  in stm32mp_ddr_enable_axi_port()
106 	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,  in stm32mp_ddr_enable_axi_port()
118 	VERBOSE("[0x%lx] pctrl_0 = 0x%x\n", (uintptr_t)&ctl->pctrl_0,  in stm32mp_ddr_disable_axi_port()
124 	VERBOSE("[0x%lx] pctrl_1 = 0x%x\n", (uintptr_t)&ctl->pctrl_1,  in stm32mp_ddr_disable_axi_port()
136 		VERBOSE("[0x%lx] pstat = 0x%x ",  in stm32mp_ddr_disable_axi_port()
154 	VERBOSE("[0x%lx] dbg1 = 0x%x\n",  in stm32mp_ddr_enable_host_interface()
166 	VERBOSE("[0x%lx] dbg1 = 0x%x\n",  in stm32mp_ddr_disable_host_interface()
183 		VERBOSE("[0x%lx] dbgcam = 0x%x ",  in stm32mp_ddr_disable_host_interface()
206 	VERBOSE("[0x%lx] pwrctl = 0x%x\n",  in stm32mp_ddr_sw_selfref_entry()
234 	VERBOSE("[0x%lx] pwrctl = 0x%x\n",  in stm32mp_ddr_sw_selfref_exit()
286 	VERBOSE("[0x%lx] rfshctl3 = 0x%x\n",  in stm32mp_ddr_wait_refresh_update_done_ack()
292 		VERBOSE("[0x%lx] rfshctl3 = 0x%x ", (uintptr_t)&ctl->rfshctl3, rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()
298 	VERBOSE("[0x%lx] rfshctl3 = 0x%x\n", (uintptr_t)&ctl->rfshctl3, rfshctl3);  in stm32mp_ddr_wait_refresh_update_done_ack()