234 	uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();  in sr_ssr_set()  local
240 	mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);  in sr_ssr_set()
243 	mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_EN);  in sr_ssr_set()
253 	uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();  in sr_ssr_entry()  local
256 	if (stm32mp_ddr_disable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {  in sr_ssr_entry()
267 	disable_dfi_low_power_interface((struct stm32mp_ddrctl *)ddrctrl_base);  in sr_ssr_entry()
270 	mmio_setbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);  in sr_ssr_entry()
272 	mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_STAY_IN_SELFREF);  in sr_ssr_entry()
279 	ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, true);  in sr_ssr_entry()
298 	uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();  in sr_ssr_exit()  local
308 	ddr_activate_controller((struct stm32mp_ddrctl *)ddrctrl_base, false);  in sr_ssr_exit()
314 	mmio_clrbits_32(ddrctrl_base + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW);  in sr_ssr_exit()
321 	mmio_setbits_32(ddrctrl_base + DDRCTRL_DFILPCFG0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);  in sr_ssr_exit()
323 	stm32mp_ddr_enable_axi_port((struct stm32mp_ddrctl *)ddrctrl_base);  in sr_ssr_exit()
330 	uintptr_t ddrctrl_base = stm32mp_ddrctrl_base();  in sr_hsr_set()  local
339 	if (stm32mp_ddr_sw_selfref_entry((struct stm32mp_ddrctl *)ddrctrl_base) != 0) {  in sr_hsr_set()
342 	stm32mp_ddr_start_sw_done((struct stm32mp_ddrctl *)ddrctrl_base);  in sr_hsr_set()
344 	mmio_write_32(ddrctrl_base + DDRCTRL_HWLPCTL,  in sr_hsr_set()
348 	stm32mp_ddr_wait_sw_done_ack((struct stm32mp_ddrctl *)ddrctrl_base);  in sr_hsr_set()
349 	stm32mp_ddr_sw_selfref_exit((struct stm32mp_ddrctl *)ddrctrl_base);  in sr_hsr_set()