213 static void ddr_reset(struct stm32mp_ddr_priv *priv)  in ddr_reset()  argument
217 	mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in ddr_reset()
218 	mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,  in ddr_reset()
221 	mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,  in ddr_reset()
224 	mmio_write_32(priv->rcc + RCC_DDRCFGR,  in ddr_reset()
229 	mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in ddr_reset()
230 	mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,  in ddr_reset()
232 	mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,  in ddr_reset()
234 	mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);  in ddr_reset()
239 static void ddr_standby_reset(struct stm32mp_ddr_priv *priv)  in ddr_standby_reset()  argument
243 	mmio_write_32(priv->rcc + RCC_DDRCPCFGR,  in ddr_standby_reset()
245 	mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in ddr_standby_reset()
246 	mmio_write_32(priv->rcc + RCC_DDRPHYCAPBCFGR,  in ddr_standby_reset()
249 	mmio_write_32(priv->rcc + RCC_DDRCAPBCFGR,  in ddr_standby_reset()
253 	mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP);  in ddr_standby_reset()
254 	mmio_setbits_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);  in ddr_standby_reset()
259 static void ddr_standby_reset_release(struct stm32mp_ddr_priv *priv)  in ddr_standby_reset_release()  argument
263 	mmio_write_32(priv->rcc + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPEN | RCC_DDRCPCFGR_DDRCPLPEN);  in ddr_standby_reset_release()
264 	mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in ddr_standby_reset_release()
265 	mmio_clrbits_32(priv->rcc + RCC_DDRPHYCAPBCFGR, RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST);  in ddr_standby_reset_release()
266 	mmio_write_32(priv->rcc + RCC_DDRCFGR, RCC_DDRCFGR_DDRCFGEN | RCC_DDRCFGR_DDRCFGLPEN);  in ddr_standby_reset_release()
271 static void ddr_sysconf_configuration(struct stm32mp_ddr_priv *priv,  in ddr_sysconf_configuration()  argument
280 	mmio_write_32(priv->rcc + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN);  in ddr_sysconf_configuration()
281 	mmio_setbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in ddr_sysconf_configuration()
357 void stm32mp2_ddr_init(struct stm32mp_ddr_priv *priv,  in stm32mp2_ddr_init()  argument
383 	ddr_retdis = mmio_read_32(priv->pwr + PWR_CR11) & PWR_CR11_DDRRETDIS;  in stm32mp2_ddr_init()
392 		ddr_standby_reset(priv);  in stm32mp2_ddr_init()
395 		mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);  in stm32mp2_ddr_init()
399 		mmio_clrbits_32(priv->rcc + RCC_DDRCAPBCFGR, RCC_DDRCAPBCFGR_DDRCAPBRST);  in stm32mp2_ddr_init()
410 		mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS);  in stm32mp2_ddr_init()
412 		ddr_reset(priv);  in stm32mp2_ddr_init()
414 		ddr_sysconf_configuration(priv, config);  in stm32mp2_ddr_init()
425 	stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers);  in stm32mp2_ddr_init()
426 	stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers);  in stm32mp2_ddr_init()
427 	stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers);  in stm32mp2_ddr_init()
428 	stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers);  in stm32mp2_ddr_init()
432 		mmio_clrbits_32(priv->rcc + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRRST);  in stm32mp2_ddr_init()
434 		disable_refresh(priv->ctl);  in stm32mp2_ddr_init()
438 		ddr_standby_reset_release(priv);  in stm32mp2_ddr_init()
459 	ddr_activate_controller(priv->ctl, false);  in stm32mp2_ddr_init()
462 		struct stm32mp_ddrctl *ctl = priv->ctl;  in stm32mp2_ddr_init()
475 		restore_refresh(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl);  in stm32mp2_ddr_init()
478 	stm32mp_ddr_enable_axi_port(priv->ctl);  in stm32mp2_ddr_init()