Lines Matching refs:priv
274 static void stm32mp1_wait_operating_mode(struct stm32mp_ddr_priv *priv, uint32_t mode) in stm32mp1_wait_operating_mode() argument
285 stat = mmio_read_32((uintptr_t)&priv->ctl->stat); in stm32mp1_wait_operating_mode()
289 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
319 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
323 static void stm32mp1_mode_register_write(struct stm32mp_ddr_priv *priv, uint8_t addr, in stm32mp1_mode_register_write() argument
336 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
349 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
351 (uintptr_t)&priv->ctl->mrctrl0, in stm32mp1_mode_register_write()
352 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0); in stm32mp1_mode_register_write()
353 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data); in stm32mp1_mode_register_write()
355 (uintptr_t)&priv->ctl->mrctrl1, in stm32mp1_mode_register_write()
356 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1)); in stm32mp1_mode_register_write()
366 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
368 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
374 (uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
378 static void stm32mp1_ddr3_dll_off(struct stm32mp_ddr_priv *priv) in stm32mp1_ddr3_dll_off() argument
380 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1); in stm32mp1_ddr3_dll_off()
381 uint32_t mr2 = mmio_read_32((uintptr_t)&priv->phy->mr2); in stm32mp1_ddr3_dll_off()
391 mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF); in stm32mp1_ddr3_dll_off()
393 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
394 mmio_read_32((uintptr_t)&priv->ctl->dbg1)); in stm32mp1_ddr3_dll_off()
405 dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam); in stm32mp1_ddr3_dll_off()
407 (uintptr_t)&priv->ctl->dbgcam, dbgcam); in stm32mp1_ddr3_dll_off()
419 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
434 stm32mp1_mode_register_write(priv, 2, mr2); in stm32mp1_ddr3_dll_off()
444 stm32mp1_mode_register_write(priv, 1, mr1); in stm32mp1_ddr3_dll_off()
451 mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
454 (uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
455 mmio_read_32((uintptr_t)&priv->ctl->pwrctl)); in stm32mp1_ddr3_dll_off()
463 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_SR); in stm32mp1_ddr3_dll_off()
469 stm32mp_ddr_start_sw_done(priv->ctl); in stm32mp1_ddr3_dll_off()
471 mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE); in stm32mp1_ddr3_dll_off()
473 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr3_dll_off()
474 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr3_dll_off()
476 stm32mp_ddr_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr3_dll_off()
488 mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
491 mmio_setbits_32((uintptr_t)&priv->phy->dllgcr, in stm32mp1_ddr3_dll_off()
495 mmio_setbits_32((uintptr_t)&priv->phy->acdllcr, DDRPHYC_ACDLLCR_DLLDIS); in stm32mp1_ddr3_dll_off()
497 mmio_setbits_32((uintptr_t)&priv->phy->dx0dllcr, in stm32mp1_ddr3_dll_off()
499 mmio_setbits_32((uintptr_t)&priv->phy->dx1dllcr, in stm32mp1_ddr3_dll_off()
502 mmio_setbits_32((uintptr_t)&priv->phy->dx2dllcr, in stm32mp1_ddr3_dll_off()
504 mmio_setbits_32((uintptr_t)&priv->phy->dx3dllcr, in stm32mp1_ddr3_dll_off()
509 stm32mp_ddr_sw_selfref_exit(priv->ctl); in stm32mp1_ddr3_dll_off()
510 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr3_dll_off()
524 stm32mp_ddr_enable_host_interface(priv->ctl); in stm32mp1_ddr3_dll_off()
556 void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv, in stm32mp1_ddr_init() argument
588 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
589 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
590 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
591 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
592 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
593 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
596 if (stm32mp1_ddr_clk_enable(priv, config->info.speed) != 0) { in stm32mp1_ddr_init()
602 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
603 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
608 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
616 mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
619 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
620 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
622 stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers); in stm32mp1_ddr_init()
629 mmio_clrbits_32((uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
632 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
633 mmio_read_32((uintptr_t)&priv->ctl->mstr)); in stm32mp1_ddr_init()
636 stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers); in stm32mp1_ddr_init()
637 stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers); in stm32mp1_ddr_init()
640 mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
644 (uintptr_t)&priv->ctl->init0, in stm32mp1_ddr_init()
645 mmio_read_32((uintptr_t)&priv->ctl->init0)); in stm32mp1_ddr_init()
647 stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers); in stm32mp1_ddr_init()
650 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
651 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
652 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
658 stm32mp_ddr_set_reg(priv, REGPHY_REG, &config->p_reg, ddr_registers); in stm32mp1_ddr_init()
659 stm32mp_ddr_set_reg(priv, REGPHY_TIMING, &config->p_timing, ddr_registers); in stm32mp1_ddr_init()
666 mmio_clrbits_32((uintptr_t)&priv->phy->mr1, BIT(0)); in stm32mp1_ddr_init()
668 (uintptr_t)&priv->phy->mr1, in stm32mp1_ddr_init()
669 mmio_read_32((uintptr_t)&priv->phy->mr1)); in stm32mp1_ddr_init()
676 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
691 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
697 stm32mp_ddr_start_sw_done(priv->ctl); in stm32mp1_ddr_init()
699 mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
702 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
703 mmio_read_32((uintptr_t)&priv->ctl->dfimisc)); in stm32mp1_ddr_init()
705 stm32mp_ddr_wait_sw_done_ack(priv->ctl); in stm32mp1_ddr_init()
713 stm32mp1_wait_operating_mode(priv, DDRCTRL_STAT_OPERATING_MODE_NORMAL); in stm32mp1_ddr_init()
717 stm32mp1_ddr3_dll_off(priv); in stm32mp1_ddr_init()
728 stm32mp1_refresh_disable(priv->ctl); in stm32mp1_ddr_init()
746 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
749 stm32mp1_ddrphy_idone_wait(priv->phy); in stm32mp1_ddr_init()
754 stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, in stm32mp1_ddr_init()
757 stm32mp_ddr_enable_axi_port(priv->ctl); in stm32mp1_ddr_init()