221 		VERBOSE("  > [0x%lx] pgsr = 0x%x &\n",  in stm32mp1_ddrphy_idone_wait()
229 			VERBOSE("DQS Gate Trainig Error\n");  in stm32mp1_ddrphy_idone_wait()
234 			VERBOSE("DQS Gate Trainig Intermittent Error\n");  in stm32mp1_ddrphy_idone_wait()
239 			VERBOSE("DQS Drift Error\n");  in stm32mp1_ddrphy_idone_wait()
244 			VERBOSE("Read Valid Training Error\n");  in stm32mp1_ddrphy_idone_wait()
249 			VERBOSE("Read Valid Training Intermittent Error\n");  in stm32mp1_ddrphy_idone_wait()
253 	VERBOSE("\n[0x%lx] pgsr = 0x%x\n",  in stm32mp1_ddrphy_idone_wait()
262 	VERBOSE("[0x%lx] pir = 0x%x -> 0x%x\n",  in stm32mp1_ddrphy_init()
288 		VERBOSE("[0x%lx] stat = 0x%x\n",  in stm32mp1_wait_operating_mode()
318 	VERBOSE("[0x%lx] stat = 0x%x\n",  in stm32mp1_wait_operating_mode()
328 	VERBOSE("MRS: %d = %x\n", addr, data);  in stm32mp1_mode_register_write()
350 	VERBOSE("[0x%lx] mrctrl0 = 0x%x (0x%x)\n",  in stm32mp1_mode_register_write()
354 	VERBOSE("[0x%lx] mrctrl1 = 0x%x\n",  in stm32mp1_mode_register_write()
373 	VERBOSE("[0x%lx] mrctrl0 = 0x%x\n",  in stm32mp1_mode_register_write()
384 	VERBOSE("mr1: 0x%x\n", mr1);  in stm32mp1_ddr3_dll_off()
385 	VERBOSE("mr2: 0x%x\n", mr2);  in stm32mp1_ddr3_dll_off()
392 	VERBOSE("[0x%lx] dbg1 = 0x%x\n",  in stm32mp1_ddr3_dll_off()
406 		VERBOSE("[0x%lx] dbgcam = 0x%x\n",  in stm32mp1_ddr3_dll_off()
453 	VERBOSE("[0x%lx] pwrctl = 0x%x\n",  in stm32mp1_ddr3_dll_off()
472 	VERBOSE("[0x%lx] mstr = 0x%x\n",  in stm32mp1_ddr3_dll_off()
576 	VERBOSE("name = %s\n", config->info.name);  in stm32mp1_ddr_init()
577 	VERBOSE("speed = %u kHz\n", config->info.speed);  in stm32mp1_ddr_init()
578 	VERBOSE("size  = 0x%x\n", config->info.size);  in stm32mp1_ddr_init()
618 	VERBOSE("[0x%lx] dfimisc = 0x%x\n",  in stm32mp1_ddr_init()
628 		VERBOSE("deactivate DLL OFF in mstr\n");  in stm32mp1_ddr_init()
631 		VERBOSE("[0x%lx] mstr = 0x%x\n",  in stm32mp1_ddr_init()
643 	VERBOSE("[0x%lx] init0 = 0x%x\n",  in stm32mp1_ddr_init()
665 		VERBOSE("deactivate DLL OFF in mr1\n");  in stm32mp1_ddr_init()
667 		VERBOSE("[0x%lx] mr1 = 0x%x\n",  in stm32mp1_ddr_init()
701 	VERBOSE("[0x%lx] dfimisc = 0x%x\n",  in stm32mp1_ddr_init()
720 	VERBOSE("DDR DQS training : ");  in stm32mp1_ddr_init()