34 #define _SAES_DINR			0x08U  macro
608 		mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 0U]);  in stm32_saes_update_assodata()
609 		mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 1U]);  in stm32_saes_update_assodata()
610 		mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 2U]);  in stm32_saes_update_assodata()
611 		mmio_write_32(ctx->base + _SAES_DINR, data_u32[w + 3U]);  in stm32_saes_update_assodata()
689 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);  in stm32_saes_update_load()
690 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);  in stm32_saes_update_load()
691 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);  in stm32_saes_update_load()
692 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);  in stm32_saes_update_load()
719 		mmio_write_32(ctx->base + _SAES_DINR, block_in[0U]);  in stm32_saes_update_load()
720 		mmio_write_32(ctx->base + _SAES_DINR, block_in[1U]);  in stm32_saes_update_load()
721 		mmio_write_32(ctx->base + _SAES_DINR, block_in[2U]);  in stm32_saes_update_load()
722 		mmio_write_32(ctx->base + _SAES_DINR, block_in[3U]);  in stm32_saes_update_load()
779 	mmio_write_32(ctx->base + _SAES_DINR, 0);  in stm32_saes_final()
780 	mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len);  in stm32_saes_final()
781 	mmio_write_32(ctx->base + _SAES_DINR, 0);  in stm32_saes_final()
782 	mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len);  in stm32_saes_final()
865 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 0U]);  in stm32_saes_update()
866 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 1U]);  in stm32_saes_update()
867 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 2U]);  in stm32_saes_update()
868 		mmio_write_32(ctx->base + _SAES_DINR, data_in_u32[w + 3U]);  in stm32_saes_update()