74 	struct stm32_pll_vco vco;  member
1195 				       struct stm32_pll_vco *vco,  in clk_stm32_pll_compute_cfgr1()  argument
1198 	uint32_t divm = vco->div_mn[PLL_CFG_M];  in clk_stm32_pll_compute_cfgr1()
1199 	uint32_t divn = vco->div_mn[PLL_CFG_N];  in clk_stm32_pll_compute_cfgr1()
1236 				     struct stm32_pll_vco *vco)  in clk_stm32_pll_config_vco()  argument
1241 	if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) {  in clk_stm32_pll_config_vco()
1253 	mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);  in clk_stm32_pll_config_vco()
1259 				     struct stm32_pll_vco *vco)  in clk_stm32_pll_config_csg()  argument
1267 	if (!vco->csg_enabled) {  in clk_stm32_pll_config_csg()
1271 	mod_per = vco->csg[PLL_CSG_MOD_PER];  in clk_stm32_pll_config_csg()
1272 	inc_step = vco->csg[PLL_CSG_INC_STEP];  in clk_stm32_pll_config_csg()
1273 	sscg_mode = vco->csg[PLL_CSG_SSCG_MODE];  in clk_stm32_pll_config_csg()
1323 	uint32_t src =  pll2->vco.src;  in clk_compute_pll1_settings()
1372 				unsigned long long vco;  in clk_compute_pll1_settings()  local
1378 				vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX);  in clk_compute_pll1_settings()
1380 				if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) {  in clk_compute_pll1_settings()
1385 				freq = vco / (divp + 1U);  in clk_compute_pll1_settings()
1393 					pll1->vco.src = src;  in clk_compute_pll1_settings()
1394 					pll1->vco.status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_PLLON;  in clk_compute_pll1_settings()
1395 					pll1->vco.div_mn[PLL_CFG_M] = divm - 1U;  in clk_compute_pll1_settings()
1396 					pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn;  in clk_compute_pll1_settings()
1397 					pll1->vco.frac = (uint32_t)frac;  in clk_compute_pll1_settings()
1516 	ret = stm32_clk_configure_mux(priv, pll_conf->vco.src);  in _clk_stm32_pll_init()
1534 	clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1536 	clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco);  in _clk_stm32_pll_init()
1552 	if (pll_conf->vco.status != 0U) {  in clk_stm32_pll_init()
2187 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco)  in clk_stm32_load_vco_config()  argument
2191 	err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn);  in clk_stm32_load_vco_config()
2196 	err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg);  in clk_stm32_load_vco_config()
2198 	vco->csg_enabled = (err == 0);  in clk_stm32_load_vco_config()
2208 	vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON;  in clk_stm32_load_vco_config()
2210 	vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0);  in clk_stm32_load_vco_config()
2212 	vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX);  in clk_stm32_load_vco_config()
2257 	err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco);  in clk_stm32_parse_pll_fdt()