Lines Matching refs:priv
897 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx, in clk_oscillator_check_bypass() argument
900 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx); in clk_oscillator_check_bypass()
908 address = priv->base + bypass_data->offset; in clk_oscillator_check_bypass()
916 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) in stm32_enable_oscillator_hse() argument
918 struct stm32_clk_platdata *pdata = priv->pdata; in stm32_enable_oscillator_hse()
924 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { in stm32_enable_oscillator_hse()
928 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); in stm32_enable_oscillator_hse()
930 _clk_stm32_enable(priv, _CK_HSE); in stm32_enable_oscillator_hse()
933 clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass); in stm32_enable_oscillator_hse()
936 clk_oscillator_set_css(priv, _CK_HSE, css); in stm32_enable_oscillator_hse()
939 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) in stm32_enable_oscillator_lse() argument
941 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); in stm32_enable_oscillator_lse()
942 struct stm32_clk_platdata *pdata = priv->pdata; in stm32_enable_oscillator_lse()
948 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { in stm32_enable_oscillator_lse()
953 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) { in stm32_enable_oscillator_lse()
957 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); in stm32_enable_oscillator_lse()
959 clk_oscillator_set_drive(priv, _CK_LSE, drive); in stm32_enable_oscillator_lse()
961 _clk_stm32_gate_enable(priv, osc_data->gate_id); in stm32_enable_oscillator_lse()
1011 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv) in stm32_clk_oscillators_lse_set_css() argument
1013 struct stm32_clk_platdata *pdata = priv->pdata; in stm32_clk_oscillators_lse_set_css()
1016 clk_oscillator_set_css(priv, _CK_LSE, osci->css); in stm32_clk_oscillators_lse_set_css()
1024 struct stm32_clk_priv *priv = clk_stm32_get_priv(); in stm32mp1_come_back_to_hsi() local
1027 ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI); in stm32mp1_come_back_to_hsi()
1032 ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI); in stm32mp1_come_back_to_hsi()
1037 ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI); in stm32mp1_come_back_to_hsi()
1045 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) in stm32_clk_configure_clk_get_binding_id() argument
1049 return clk_get_index(priv, binding_id); in stm32_clk_configure_clk_get_binding_id()
1052 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) in stm32_clk_configure_clk() argument
1059 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); in stm32_clk_configure_clk()
1064 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); in stm32_clk_configure_clk()
1070 clk_stm32_enable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1072 clk_stm32_disable_call_ops(priv, clk_id); in stm32_clk_configure_clk()
1078 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) in stm32_clk_configure_mux() argument
1083 return clk_mux_set_parent(priv, mux, sel); in stm32_clk_configure_mux()
1086 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) in stm32_clk_dividers_configure() argument
1088 struct stm32_clk_platdata *pdata = priv->pdata; in stm32_clk_dividers_configure()
1100 ret = clk_stm32_set_div(priv, div_id, div_n); in stm32_clk_dividers_configure()
1109 static int stm32_clk_source_configure(struct stm32_clk_priv *priv) in stm32_clk_source_configure() argument
1111 struct stm32_clk_platdata *pdata = priv->pdata; in stm32_clk_source_configure()
1135 ret = stm32_clk_configure_mux(priv, cmd_data); in stm32_clk_source_configure()
1139 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); in stm32_clk_source_configure()
1142 if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) { in stm32_clk_source_configure()
1147 ret = stm32_clk_configure_clk(priv, cmd_data); in stm32_clk_source_configure()
1166 ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED); in stm32_clk_source_configure()
1175 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id) in stm32_clk_stgen_configure() argument
1179 stgen_freq = _clk_stm32_get_rate(priv, id); in stm32_clk_stgen_configure()
1193 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv, in clk_stm32_pll_compute_cfgr1() argument
1203 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); in clk_stm32_pll_compute_cfgr1()
1234 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv, in clk_stm32_pll_config_vco() argument
1238 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_vco()
1241 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) { in clk_stm32_pll_config_vco()
1257 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, in clk_stm32_pll_config_csg() argument
1261 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_csg()
1283 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll, in clk_stm32_pll_config_out() argument
1286 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_out()
1296 struct stm32_clk_priv *priv = clk_stm32_get_priv(); in clk_stm32_pll_get_pdata() local
1297 struct stm32_clk_platdata *pdata = priv->pdata; in clk_stm32_pll_get_pdata()
1317 struct stm32_clk_priv *priv = clk_stm32_get_priv(); in clk_compute_pll1_settings() local
1328 input_freq = _clk_stm32_get_rate(priv, _CK_HSI); in clk_compute_pll1_settings()
1331 input_freq = _clk_stm32_get_rate(priv, _CK_HSE); in clk_compute_pll1_settings()
1419 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_is_enabled() argument
1421 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_is_enabled()
1426 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_set_on() argument
1428 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_set_on()
1435 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_set_off() argument
1437 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_set_off()
1446 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, in _clk_stm32_pll_wait_ready_on() argument
1449 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_wait_ready_on()
1464 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, in _clk_stm32_pll_wait_ready_off() argument
1467 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_wait_ready_off()
1482 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_enable() argument
1484 if (_clk_stm32_pll_is_enabled(priv, pll)) { in _clk_stm32_pll_enable()
1489 _clk_stm32_pll_set_on(priv, pll); in _clk_stm32_pll_enable()
1492 return _clk_stm32_pll_wait_ready_on(priv, pll); in _clk_stm32_pll_enable()
1495 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) in _clk_stm32_pll_disable() argument
1497 if (!_clk_stm32_pll_is_enabled(priv, pll)) { in _clk_stm32_pll_disable()
1502 _clk_stm32_pll_set_off(priv, pll); in _clk_stm32_pll_disable()
1505 _clk_stm32_pll_wait_ready_off(priv, pll); in _clk_stm32_pll_disable()
1508 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, in _clk_stm32_pll_init() argument
1512 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in _clk_stm32_pll_init()
1516 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src); in _clk_stm32_pll_init()
1523 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); in _clk_stm32_pll_init()
1532 _clk_stm32_pll_disable(priv, pll); in _clk_stm32_pll_init()
1534 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); in _clk_stm32_pll_init()
1535 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); in _clk_stm32_pll_init()
1536 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco); in _clk_stm32_pll_init()
1538 ret = _clk_stm32_pll_enable(priv, pll); in _clk_stm32_pll_init()
1548 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) in clk_stm32_pll_init() argument
1553 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); in clk_stm32_pll_init()
1559 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv) in stm32_clk_pll_configure() argument
1563 err = clk_stm32_pll_init(priv, _PLL1); in stm32_clk_pll_configure()
1568 err = clk_stm32_pll_init(priv, _PLL2); in stm32_clk_pll_configure()
1573 err = clk_stm32_pll_init(priv, _PLL3); in stm32_clk_pll_configure()
1578 err = clk_stm32_pll_init(priv, _PLL4); in stm32_clk_pll_configure()
1586 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) in stm32_clk_oscillators_wait_lse_ready() argument
1590 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { in stm32_clk_oscillators_wait_lse_ready()
1591 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); in stm32_clk_oscillators_wait_lse_ready()
1597 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) in stm32_clk_oscillators_enable() argument
1599 stm32_enable_oscillator_hse(priv); in stm32_clk_oscillators_enable()
1600 stm32_enable_oscillator_lse(priv); in stm32_clk_oscillators_enable()
1601 _clk_stm32_enable(priv, _CK_LSI); in stm32_clk_oscillators_enable()
1602 _clk_stm32_enable(priv, _CK_CSI); in stm32_clk_oscillators_enable()
1605 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv) in stm32_clk_hsidiv_configure() argument
1607 return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI)); in stm32_clk_hsidiv_configure()
1611 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p) in stm32mp1_clk_is_pll4_used_by_bootrom() argument
1623 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p) in stm32mp1_clk_check_usb_conflict() argument
1632 _usbo_p = _clk_stm32_get_parent(priv, _USBO_K); in stm32mp1_clk_check_usb_conflict()
1633 _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); in stm32mp1_clk_check_usb_conflict()
1699 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, in clk_stm32_pll_recalc_rate() argument
1702 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_stm32_pll_recalc_rate()
1705 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_recalc_rate()
1737 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) in clk_stm32_pll_is_enabled() argument
1739 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_stm32_pll_is_enabled()
1743 return _clk_stm32_pll_is_enabled(priv, pll); in clk_stm32_pll_is_enabled()
1746 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) in clk_stm32_pll_enable() argument
1748 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_stm32_pll_enable()
1752 return _clk_stm32_pll_enable(priv, pll); in clk_stm32_pll_enable()
1755 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) in clk_stm32_pll_disable() argument
1757 const struct clk_stm32 *clk = _clk_get(priv, id); in clk_stm32_pll_disable()
1761 _clk_stm32_pll_disable(priv, pll); in clk_stm32_pll_disable()
1786 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv, in clk_stm32_composite_recalc_rate() argument
1789 const struct clk_stm32 *clk = _clk_get(priv, idx); in clk_stm32_composite_recalc_rate()
1792 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate); in clk_stm32_composite_recalc_rate()
1795 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx) in clk_stm32_composite_gate_is_enabled() argument
1797 const struct clk_stm32 *clk = _clk_get(priv, idx); in clk_stm32_composite_gate_is_enabled()
1800 return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id); in clk_stm32_composite_gate_is_enabled()
1803 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx) in clk_stm32_composite_gate_enable() argument
1805 const struct clk_stm32 *clk = _clk_get(priv, idx); in clk_stm32_composite_gate_enable()
1808 return _clk_stm32_gate_enable(priv, composite_cfg->gate_id); in clk_stm32_composite_gate_enable()
1811 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx) in clk_stm32_composite_gate_disable() argument
1813 const struct clk_stm32 *clk = _clk_get(priv, idx); in clk_stm32_composite_gate_disable()
1816 _clk_stm32_gate_disable(priv, composite_cfg->gate_id); in clk_stm32_composite_gate_disable()
2025 struct stm32_clk_priv *priv = clk_stm32_get_priv(); in stm32mp1_init_clock_tree() local
2029 int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); in stm32mp1_init_clock_tree()
2030 int usbo_p = _clk_stm32_get_parent(priv, _USBO_K); in stm32mp1_init_clock_tree()
2033 pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p); in stm32mp1_init_clock_tree()
2040 stm32_clk_oscillators_enable(priv); in stm32mp1_init_clock_tree()
2048 ret = stm32_clk_hsidiv_configure(priv); in stm32mp1_init_clock_tree()
2053 ret = stm32_clk_stgen_configure(priv, _STGENC); in stm32mp1_init_clock_tree()
2058 ret = stm32_clk_dividers_configure(priv); in stm32mp1_init_clock_tree()
2063 ret = stm32_clk_pll_configure(priv); in stm32mp1_init_clock_tree()
2069 ret = stm32_clk_oscillators_wait_lse_ready(priv); in stm32mp1_init_clock_tree()
2075 ret = stm32_clk_source_configure(priv); in stm32mp1_init_clock_tree()
2081 ret = stm32_clk_oscillators_lse_set_css(priv); in stm32mp1_init_clock_tree()
2087 ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p); in stm32mp1_init_clock_tree()
2093 ret = stm32_clk_stgen_configure(priv, _STGENC); in stm32mp1_init_clock_tree()
2099 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, in stm32mp1_init_clock_tree()