47 #define IIC_ICSR			(IIC_DVFS_BASE + 0x0008U)  macro
241 			if ((mmio_read_8(IIC_ICSR) & ICSR_DTE) == ICSR_DTE) {  in rcar_avs_setting()
263 			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {  in rcar_avs_setting()
267 				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
285 			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {  in rcar_avs_setting()
299 				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
316 			if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {  in rcar_avs_setting()
320 				mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
329 		if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {  in rcar_avs_setting()
338 		mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
347 		mmio_write_8(IIC_ICSR, (mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
359 		mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
366 		if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) {  in rcar_avs_setting()
370 			mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR)  in rcar_avs_setting()
378 		if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) {  in rcar_avs_setting()
452 	if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) {  in avs_check_error()
464 	} else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) {  in avs_check_error()
556 	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));  in avs_read_pmic_reg()
564 	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));  in avs_read_pmic_reg()
583 	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));  in avs_read_pmic_reg()
591 	mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t) (~ICSR_WAIT));  in avs_read_pmic_reg()
624 		if ((mmio_read_8(IIC_ICSR) & bit_pos) == bit_val)  in avs_poll()