23 static struct space_timing_params tr_res = {  variable
376 	tr_res.cdd.rr = cdd_rr;  in read_cdds()
377 	tr_res.cdd.ww = cdd_ww;  in read_cdds()
378 	tr_res.cdd.rw = is_lpddr4() ?  in read_cdds()
381 	tr_res.cdd.wr = is_lpddr4() ?  in read_cdds()
432 		if (cdd_rr > tr_res.cdd.rr) {  in read_cdds()
433 			tr_res.cdd.rr = cdd_rr;  in read_cdds()
435 		if (cdd_rw > tr_res.cdd.rw) {  in read_cdds()
436 			tr_res.cdd.rw = cdd_rw;  in read_cdds()
438 		if (cdd_wr > tr_res.cdd.wr) {  in read_cdds()
439 			tr_res.cdd.wr = cdd_wr;  in read_cdds()
441 		if (cdd_ww > tr_res.cdd.ww) {  in read_cdds()
442 			tr_res.cdd.ww = cdd_ww;  in read_cdds()
458 		tr_res.vref_ca = get_avg_vref(rank01_vref_addr,  in read_vref_ca()
461 		tr_res.vref_ca = get_avg_vref(rank0_vref_addr,  in read_vref_ca()
477 		tr_res.vref_dq = get_avg_vref(rank01_vref_addr,  in read_vref_dq()
480 		tr_res.vref_dq = get_avg_vref(rank0_vref_addr,  in read_vref_dq()
536 	tr_res.tphy_wrdata_delay = tctrl_delay + 6U + burst_length +  in compute_tphy_wrdata_delay()
538 	tr_res.tphy_wrdata_delay = (tr_res.tphy_wrdata_delay / 2U) +  in compute_tphy_wrdata_delay()
539 				   (tr_res.tphy_wrdata_delay % 2U);  in compute_tphy_wrdata_delay()
553 	delta = (uint8_t)((tr_res.cdd.rw + (tr_res.cdd.rw % 2U)) / 2U);  in adjust_ddrc_config()
558 	delta = (uint8_t)((tr_res.cdd.ww + (tr_res.cdd.ww % 2U)) / 2U);  in adjust_ddrc_config()
568 		mmio_clrsetbits_32(DDRC_BASE + OFFSET_DDRC_INIT6, INIT6_MR5_MASK, tr_res.vref_ca);  in adjust_ddrc_config()
571 		mmio_clrsetbits_32(DDRC_BASE + OFFSET_DDRC_INIT7, INIT7_MR6_MASK, tr_res.vref_dq);  in adjust_ddrc_config()
577 			   (((uint32_t)tr_res.tphy_wrdata_delay) << DFITMG1_WRDATA_DELAY_POS));  in adjust_ddrc_config()
590 		rd_gap_new = (uint8_t)((rd_gap_ct + tr_res.cdd.rr +  in adjust_ddrc_config()
591 					(tr_res.cdd.rr % 2U)) / 2U);  in adjust_ddrc_config()
607 		wr_gap_new = (uint8_t)((wr_gap_ct + tr_res.cdd.ww +  in adjust_ddrc_config()
608 					(tr_res.cdd.ww % 2U)) / 2U);  in adjust_ddrc_config()