Lines Matching defs:ddr4r2d
674 struct ddr4r2d { struct
675 uint8_t reserved00;
676 uint8_t msg_misc;
677 uint16_t pmu_revision;
678 uint8_t pstate;
679 uint8_t pll_bypass_en;
680 uint16_t dramfreq;
681 uint8_t dfi_freq_ratio;
682 uint8_t bpznres_val;
683 uint8_t phy_odt_impedance;
684 uint8_t phy_drv_impedance;
685 uint8_t phy_vref;
686 uint8_t dram_type;
687 uint8_t disabled_dbyte;
688 uint8_t enabled_dqs;
689 uint8_t cs_present;
690 uint8_t cs_present_d0;
691 uint8_t cs_present_d1;
692 uint8_t addr_mirror;
693 uint8_t cs_test_fail;
694 uint8_t phy_cfg;
695 uint16_t sequence_ctrl;
696 uint8_t hdt_ctrl;
697 uint8_t rx2d_train_opt;
698 uint8_t tx2d_train_opt;
699 uint8_t share2dvref_result;
700 uint8_t delay_weight2d;
701 uint8_t voltage_weight2d;
702 uint8_t reserved1e[0x22-0x1e];
703 uint16_t phy_config_override;
704 uint8_t dfimrlmargin;
705 uint8_t r0_rx_clk_dly_margin;
706 uint8_t r0_vref_dac_margin;
707 uint8_t r0_tx_dq_dly_margin;
708 uint8_t r0_device_vref_margin;
709 uint8_t reserved29[0x33-0x29];
710 uint8_t r1_rx_clk_dly_margin;
711 uint8_t r1_vref_dac_margin;
712 uint8_t r1_tx_dq_dly_margin;
713 uint8_t r1_device_vref_margin;
714 uint8_t reserved37[0x41-0x37];
715 uint8_t r2_rx_clk_dly_margin;
716 uint8_t r2_vref_dac_margin;
717 uint8_t r2_tx_dq_dly_margin;
718 uint8_t r2_device_vref_margin;
719 uint8_t reserved45[0x4f - 0x45];
720 uint8_t r3_rx_clk_dly_margin;
721 uint8_t r3_vref_dac_margin;
722 uint8_t r3_tx_dq_dly_margin;
723 uint8_t r3_device_vref_margin;
724 uint8_t reserved53[0x5e - 0x53];
725 uint16_t mr0;
726 uint16_t mr1;
727 uint16_t mr2;
728 uint16_t mr3;
729 uint16_t mr4;
730 uint16_t mr5;
731 uint16_t mr6;
732 uint8_t x16present;
733 uint8_t cs_setup_gddec;
734 uint16_t rtt_nom_wr_park0;
735 uint16_t rtt_nom_wr_park1;
736 uint16_t rtt_nom_wr_park2;
737 uint16_t rtt_nom_wr_park3;
738 uint16_t rtt_nom_wr_park4;
739 uint16_t rtt_nom_wr_park5;
740 uint16_t rtt_nom_wr_park6;
741 uint16_t rtt_nom_wr_park7;
742 uint8_t acsm_odt_ctrl0;
743 uint8_t acsm_odt_ctrl1;
744 uint8_t acsm_odt_ctrl2;
745 uint8_t acsm_odt_ctrl3;
746 uint8_t acsm_odt_ctrl4;
747 uint8_t acsm_odt_ctrl5;
748 uint8_t acsm_odt_ctrl6;
749 uint8_t acsm_odt_ctrl7;
750 uint8_t vref_dq_r0nib0;
751 uint8_t vref_dq_r0nib1;
752 uint8_t vref_dq_r0nib2;
753 uint8_t vref_dq_r0nib3;
754 uint8_t vref_dq_r0nib4;
755 uint8_t vref_dq_r0nib5;
756 uint8_t vref_dq_r0nib6;
757 uint8_t vref_dq_r0nib7;
758 uint8_t vref_dq_r0nib8;
759 uint8_t vref_dq_r0nib9;
760 uint8_t vref_dq_r0nib10;
761 uint8_t vref_dq_r0nib11;
762 uint8_t vref_dq_r0nib12;
763 uint8_t vref_dq_r0nib13;
764 uint8_t vref_dq_r0nib14;
765 uint8_t vref_dq_r0nib15;
766 uint8_t vref_dq_r0nib16;
767 uint8_t vref_dq_r0nib17;
768 uint8_t vref_dq_r0nib18;
769 uint8_t vref_dq_r0nib19;
770 uint8_t vref_dq_r1nib0;
771 uint8_t vref_dq_r1nib1;
772 uint8_t vref_dq_r1nib2;
773 uint8_t vref_dq_r1nib3;
774 uint8_t vref_dq_r1nib4;
775 uint8_t vref_dq_r1nib5;
776 uint8_t vref_dq_r1nib6;
777 uint8_t vref_dq_r1nib7;
778 uint8_t vref_dq_r1nib8;
779 uint8_t vref_dq_r1nib9;
780 uint8_t vref_dq_r1nib10;
781 uint8_t vref_dq_r1nib11;
782 uint8_t vref_dq_r1nib12;
783 uint8_t vref_dq_r1nib13;
784 uint8_t vref_dq_r1nib14;
785 uint8_t vref_dq_r1nib15;
786 uint8_t vref_dq_r1nib16;
787 uint8_t vref_dq_r1nib17;
788 uint8_t vref_dq_r1nib18;
789 uint8_t vref_dq_r1nib19;
790 uint8_t vref_dq_r2nib0;
791 uint8_t vref_dq_r2nib1;
792 uint8_t vref_dq_r2nib2;
793 uint8_t vref_dq_r2nib3;
794 uint8_t vref_dq_r2nib4;
795 uint8_t vref_dq_r2nib5;
796 uint8_t vref_dq_r2nib6;
797 uint8_t vref_dq_r2nib7;
798 uint8_t vref_dq_r2nib8;
799 uint8_t vref_dq_r2nib9;
800 uint8_t vref_dq_r2nib10;
801 uint8_t vref_dq_r2nib11;
802 uint8_t vref_dq_r2nib12;
803 uint8_t vref_dq_r2nib13;
804 uint8_t vref_dq_r2nib14;
805 uint8_t vref_dq_r2nib15;
806 uint8_t vref_dq_r2nib16;
807 uint8_t vref_dq_r2nib17;
808 uint8_t vref_dq_r2nib18;
809 uint8_t vref_dq_r2nib19;
810 uint8_t vref_dq_r3nib0;
811 uint8_t vref_dq_r3nib1;
812 uint8_t vref_dq_r3nib2;
813 uint8_t vref_dq_r3nib3;
814 uint8_t vref_dq_r3nib4;
815 uint8_t vref_dq_r3nib5;
816 uint8_t vref_dq_r3nib6;
817 uint8_t vref_dq_r3nib7;
818 uint8_t vref_dq_r3nib8;
819 uint8_t vref_dq_r3nib9;
820 uint8_t vref_dq_r3nib10;
821 uint8_t vref_dq_r3nib11;
822 uint8_t vref_dq_r3nib12;
823 uint8_t vref_dq_r3nib13;
824 uint8_t vref_dq_r3nib14;
825 uint8_t vref_dq_r3nib15;
826 uint8_t vref_dq_r3nib16;
827 uint8_t vref_dq_r3nib17;
828 uint8_t vref_dq_r3nib18;
829 uint8_t vref_dq_r3nib19;
830 uint8_t f0rc00_d0;
831 uint8_t f0rc01_d0;
832 uint8_t f0rc02_d0;
833 uint8_t f0rc03_d0;
834 uint8_t f0rc04_d0;
835 uint8_t f0rc05_d0;
836 uint8_t f0rc06_d0;
837 uint8_t f0rc07_d0;
838 uint8_t f0rc08_d0;
839 uint8_t f0rc09_d0;
840 uint8_t f0rc0a_d0;
841 uint8_t f0rc0b_d0;
842 uint8_t f0rc0c_d0;
843 uint8_t f0rc0d_d0;
844 uint8_t f0rc0e_d0;
845 uint8_t f0rc0f_d0;
846 uint8_t f0rc1x_d0;
847 uint8_t f0rc2x_d0;
848 uint8_t f0rc3x_d0;
849 uint8_t f0rc4x_d0;
850 uint8_t f0rc5x_d0;
851 uint8_t f0rc6x_d0;
852 uint8_t f0rc7x_d0;
853 uint8_t f0rc8x_d0;
854 uint8_t f0rc9x_d0;
855 uint8_t f0rcax_d0;
856 uint8_t f0rcbx_d0;
857 uint8_t f1rc00_d0;
858 uint8_t f1rc01_d0;
859 uint8_t f1rc02_d0;
860 uint8_t f1rc03_d0;
861 uint8_t f1rc04_d0;
862 uint8_t f1rc05_d0;
863 uint8_t f1rc06_d0;
864 uint8_t f1rc07_d0;
865 uint8_t f1rc08_d0;
866 uint8_t f1rc09_d0;
867 uint8_t f1rc0a_d0;
868 uint8_t f1rc0b_d0;
869 uint8_t f1rc0c_d0;
870 uint8_t f1rc0d_d0;
871 uint8_t f1rc0e_d0;
872 uint8_t f1rc0f_d0;
873 uint8_t f1rc1x_d0;
874 uint8_t f1rc2x_d0;
875 uint8_t f1rc3x_d0;
876 uint8_t f1rc4x_d0;
877 uint8_t f1rc5x_d0;
878 uint8_t f1rc6x_d0;
879 uint8_t f1rc7x_d0;
880 uint8_t f1rc8x_d0;
881 uint8_t f1rc9x_d0;
882 uint8_t f1rcax_d0;
883 uint8_t f1rcbx_d0;
884 uint8_t f0rc00_d1;
885 uint8_t f0rc01_d1;
886 uint8_t f0rc02_d1;
887 uint8_t f0rc03_d1;
888 uint8_t f0rc04_d1;
889 uint8_t f0rc05_d1;
890 uint8_t f0rc06_d1;
891 uint8_t f0rc07_d1;
892 uint8_t f0rc08_d1;
893 uint8_t f0rc09_d1;
894 uint8_t f0rc0a_d1;
895 uint8_t f0rc0b_d1;
896 uint8_t f0rc0c_d1;
897 uint8_t f0rc0d_d1;
898 uint8_t f0rc0e_d1;
899 uint8_t f0rc0f_d1;
900 uint8_t f0rc1x_d1;
901 uint8_t f0rc2x_d1;
902 uint8_t f0rc3x_d1;
903 uint8_t f0rc4x_d1;
904 uint8_t f0rc5x_d1;
905 uint8_t f0rc6x_d1;
906 uint8_t f0rc7x_d1;
907 uint8_t f0rc8x_d1;
908 uint8_t f0rc9x_d1;
909 uint8_t f0rcax_d1;
910 uint8_t f0rcbx_d1;
911 uint8_t f1rc00_d1;
912 uint8_t f1rc01_d1;
913 uint8_t f1rc02_d1;
914 uint8_t f1rc03_d1;
915 uint8_t f1rc04_d1;
916 uint8_t f1rc05_d1;
917 uint8_t f1rc06_d1;
918 uint8_t f1rc07_d1;
919 uint8_t f1rc08_d1;
920 uint8_t f1rc09_d1;
921 uint8_t f1rc0a_d1;
922 uint8_t f1rc0b_d1;
923 uint8_t f1rc0c_d1;
924 uint8_t f1rc0d_d1;
925 uint8_t f1rc0e_d1;
926 uint8_t f1rc0f_d1;
927 uint8_t f1rc1x_d1;
928 uint8_t f1rc2x_d1;
929 uint8_t f1rc3x_d1;
930 uint8_t f1rc4x_d1;
931 uint8_t f1rc5x_d1;
932 uint8_t f1rc6x_d1;
933 uint8_t f1rc7x_d1;
934 uint8_t f1rc8x_d1;
935 uint8_t f1rc9x_d1;
936 uint8_t f1rcax_d1;
937 uint8_t f1rcbx_d1;
938 uint8_t reserved142[0x3f6 - 0x142];
939 uint16_t alt_cas_l;
940 uint8_t alt_wcas_l;
941 uint8_t d4misc;