Lines Matching refs:mclk_ps
20 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_cwl() local
22 return mclk_ps >= 1250U ? 9U : in cal_cwl()
23 (mclk_ps >= 1070U ? 10U : in cal_cwl()
24 (mclk_ps >= 935U ? 11U : in cal_cwl()
25 (mclk_ps >= 833U ? 12U : in cal_cwl()
26 (mclk_ps >= 750U ? 14U : in cal_cwl()
27 (mclk_ps >= 625U ? 16U : 18U))))); in cal_cwl()
97 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_timing_cfg() local
99 const int txp = max((int)mclk_ps * 4, 6000); in cal_timing_cfg()
574 const unsigned int mclk_ps = get_memory_clk_ps(clk); in cal_ddr_sdram_mode() local
743 if (mclk_ps >= 935) { in cal_ddr_sdram_mode()
745 } else if (mclk_ps >= 833) { in cal_ddr_sdram_mode()
749 WARN("mclk_ps not supported %d", mclk_ps); in cal_ddr_sdram_mode()
1146 unsigned int mclk_ps, in skip_caslat() argument
1275 if (mclk_ps < 625 || mclk_ps > tck_max) { in skip_caslat()
1276 ERROR("mclk %u invalid\n", mclk_ps); in skip_caslat()
1310 for (k = 0; bin[i].cl[k].tckmin_ps < mclk_ps && in skip_caslat()
1313 if (bin[i].cl[k].tckmin_ps > mclk_ps && k > 0) { in skip_caslat()
1332 const unsigned int mclk_ps = get_memory_clk_ps(clk); in compute_ddrc() local
1337 if (mclk_ps < pdimm->tckmin_x_ps) { in compute_ddrc()
1338 ERROR("DDR Clk: MCLK cycle is %u ps.\n", mclk_ps); in compute_ddrc()
1345 (pdimm->taa_ps + mclk_ps - 1) / mclk_ps; in compute_ddrc()
1350 mclk_ps, in compute_ddrc()
1366 if (cas_latency * mclk_ps > 18000) { in compute_ddrc()