Lines Matching refs:of

20 | Impact         | Leakage of secure world data to normal world                |
27 This security advisory describes the current understanding of the Trusted
28 Firmware-A (TF-A) exposure to Variant 4 of the cache speculation vulnerabilities
30 impact of these vulnerabilities on Arm systems, please refer to the `Arm
33 At the time of writing, the TF-A project is not aware of a Variant 4 exploit
35 exploit against current standard configurations of TF-A, due to the limited
37 is becoming increasingly difficult to guarantee with the introduction of complex
39 (SDEI)`_.  Also, the TF-A project does not have visibility of all
43 control bit to prevent the re-ordering of stores and loads.
45 For each affected CPU type, TF-A implements one of the two following mitigation
65 - Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
68 - Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the
71 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
82 on entry to EL3, and restores the mitigation state of the lower exception level
96 of ``SMCCC_ARCH_WORKAROUND_2`` calls and TF-A exception handling.
100 - Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of