plat/arm/arm-build-options.rst

8    DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load
10    sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build
13 -  ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
14    frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
16    should match the frame used by the Non-Secure image (normally the Linux
17    kernel). Default is true (access to the frame is allowed).
19 -  ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
20    FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled,
21    BL2 calls the platform specific function `arm_bl2_el3_plat_config_load`.
22    This function is responsible for loading, parsing, and validating the
23    FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2.
25 -  ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
27    an error is encountered during the boot process (for example, when an image
28    could not be loaded or authenticated). The watchdog is enabled in the early
29    platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The
34    have specific values at boot. This boolean option allows the Trusted Firmware
35    to have a Linux kernel image as BL33 by preparing the registers to these
37    enabled (1), the address of the Linux image must be provided via the
38    ``PRELOADED_BL33_BASE`` option. Additionally, either the ``HW_CONFIG_BASE``
39    or ``ARM_PRELOADED_DTB_BASE`` option must specify the memory location of a
43 -  ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
44    cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
45    is set, the functions which deal with MPIDR assume that the ``MT`` bit in
46    MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
49 - ``ARM_PLAT_PROVIDES_BL2_MEM_PARAMS``: This flag can be overriden to 1 in the Arm
50    platform’s ``platform.mk`` to indicate that the platform supplies its own
51    bl2_mem_params_desc.c implementation. When enabled, the common implementation
52    in ``plat/arm/common/`` is omitted, and the platform must add its own
56    for the construction of composite state-ID in the power-state parameter.
58    State-ID yet. Hence this flag is used to configure whether to use the
60    in which case the platform is configured to expect NULL in the State-ID
63 -  ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the
64    location of the ROTPK returned by the function ``plat_get_rotpk_info()``
65    for Arm platforms. Depending on the selected option, the proper private key
66    must be specified using the ``ROT_KEY`` option when building the Trusted
67    Firmware. This private key will be used by the certificate generation tool
68    to sign the BL2 and Trusted Key certificates. Available options for
71    -  ``regs`` : return the ROTPK hash stored in the Trusted root-key storage
73    -  ``devel_rsa`` : return a development public key hash embedded in the BL1
74       and BL2 binaries. This hash corresponds to the development private key
79    -  ``devel_ecdsa`` : return a development public key hash embedded in the BL1
80       and BL2 binaries. This hash corresponds to the development private key
82       is specified with ``ROT_KEY``, such as the 384 bit key in the same directory.
86       the BL1 and BL2 binaries. This key corresponds to the RSA private
91       the BL1 and BL2 binaries. This key corresponds to the EC private key
93       ECDSA key is specified by ``ROT_KEY``, such as the 384 bit key in the same directory.
95 -  ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options:
100       configured by the TrustZone controller)
103    of the translation tables library instead of version 2. It is set to 0 by
106 -  ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
107    the various partitions present in the GPT image. This support is available
108    only for the BL2 component, and it is disabled by default.
109    The following diagram shows the view of the FIP partition inside the GPT
114 For a better understanding of these options, the Arm development platform memory
115 map is explained in the :ref:`Firmware Design`.
123    incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards
124    compatible change to the MTL protocol, used for AP/SCP communication.
129    SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded
133    instead of SCPI/BOM driver for communicating with the SCP during power
139    require all the CPUs to execute the CPU specific power down sequence to
140    complete a warm reboot sequence in which only the CPUs are power cycled.
145 - ``FVP_TRUSTED_SRAM_SIZE``: Size (in kilobytes) of the Trusted SRAM region to
146   utilize when building for the FVP platform. This option defaults to 256 with
155    AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable
161  - ``NRD_CHIP_COUNT``: Configures the number of chips on a Neoverse RD platform
163    valid value greater than 1, the platform code performs required configuration
166 - ``NRD_PLATFORM_VARIANT``: Selects the variant of a Neoverse RD platform. A
169   select the appropriate platform variant for the build. The range of valid