Lines Matching refs:option
7 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured
9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
19 - ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of
23 FW_CONFIG device trees from the FIP. The option depends on RESET_TO_BL2.
25 - ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog.
34 have specific values at boot. This boolean option allows the Trusted Firmware
36 values before jumping to BL33. This option defaults to 0 (disabled). When
38 ``PRELOADED_BL33_BASE`` option. Additionally, either the ``HW_CONFIG_BASE``
39 or ``ARM_PRELOADED_DTB_BASE`` option must specify the memory location of a
40 preloaded device tree blob (DTB). This option implies
47 this flag is 0. Note that this option is not used on FVP platforms.
65 for Arm platforms. Depending on the selected option, the proper private key
66 must be specified using the ``ROT_KEY`` option when building the Trusted
97 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled)
99 - ``dram`` : Secure region in DRAM (default option when TBB is enabled,
102 - ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1
125 TF-A no longer supports earlier SCP versions. If this option is set to 1
134 management operations and for SCP RAM Firmware transfer. If this option
137 - ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of
138 CPU core on reset. This build option can be used on CSS platforms that
146 utilize when building for the FVP platform. This option defaults to 256 with
147 build option ENABLE_RME=0 and 384 for ENABLE_RME=1.
168 core count, cluster count or other peripherals. This build option is used to