Lines Matching refs:this

6 integrator can tailor this code to the system configuration to some extent,
17 diagram illustrates this:
29    this case. Please refer to section 6 "Using BL31 entrypoint as the reset
47 To enable this boot flow, compile TF-A with ``PROGRAMMABLE_RESET_ADDRESS=1``.
69 To enable this boot flow, compile TF-A with ``COLD_BOOT_SINGLE_CPU=1``. This
87 To enable this boot flow, compile TF-A with both ``COLD_BOOT_SINGLE_CPU=1``
97 processor. For this type of SoC it is desirable for the application processor
101 logic in the BL31 entry point to support this use case.
103 In this configuration, the platform's Trusted Boot Firmware must ensure that
117 SRAM and all CPU reset vectors be changed from the default ``0x0`` to this run
119 the FVP models in this way.
122 the right support in the SCP firmware, this is currently not implemented so the
131 In this configuration, BL31 uses the same reset framework and code as the one
144 In this configuration, since the CPU resets to BL31, no parameters are expected
147 location of the BL32 (if required) and BL33 images and provide this information