Lines Matching refs:handled
8 #. It should be possible to route interrupts meant to be handled by secure
17 #. It should be possible to route interrupts meant to be handled by
33 the exception level(s) it is handled in.
37 context. It is always handled in Secure-EL1.
41 current execution context. It is always handled in either Non-secure EL1
46 always handled in EL3.
134 is handled by non-secure software.
211 handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they
212 cannot be handled in EL3.
508 non-secure state. Any non-secure interrupts will be handled as described
534 If ``PSTATE.F=1`` then Secure-EL1 interrupts will be handled as per the
544 non-secure state. They should be handled through the synchronous interrupt
560 non-secure state where the interrupt should be handled e.g the SP could
574 the non-secure state where the interrupt will be handled. The Secure-EL1
577 #. **CSS=1, TEL3=0**. Non-secure interrupts are handled in the FEL in
629 lower exception level using AArch64 or AArch32 are handled.
736 the interrupt has been successfully validated and ready to be handled at a
744 so that the interrupt can be handled.
760 Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler
788 now be handled by the SP. ``x1`` is written with the value of ``elr_el3``
927 level. This will allow the non-secure interrupt to be handled in the non-secure
958 #. Secure-EL1 interrupts are handled by calling the ``tsp_common_int_handler()``
961 #. Non-secure interrupts are handled by calling the ``tsp_common_int_handler()``
996 /* The pending non-secure interrupt is handled by the interrupt handler