docs/design/cpu-specific-build-macros.rst

4 This document describes the various build options present in the CPU specific
16    of the PEs in the system need the workaround. Setting this flag to 0 provides
18    with the recommendation in the spec regarding workaround discovery.
24    CVE-2018-3639, in order to comply with the recommendation in the spec
38    in EL3 FW. This build option should be set to 1 if the target platform contains
52 in the CPU specific errata documents published by Arm:
57 errata workaround is identified by its ``ID`` as specified in the processor's
67 errata workaround build flags in the platform specific makefile. In case
126    r0p4 and onwards, this errata is enabled by default in hardware. Identical to
135    CPUs. Though the erratum is present in every revision of the CPU,
137    a chicken bit in CPUACTLR_EL1 to enable a hardware workaround.
139    workaround in software, so they should be covered anyway.
209    in r1p0.
213    is fixed in r1p1.
269    revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
287    fixed in r1p1.
291    fixed in r1p1.
295    fixed in r1p1.
340    CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
344    is present in r0p0 but there is no workaround. It is still open.
398   fixed in r0p1.
402   fixed in r0p1.
501    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
506    in r1p1.
510    in r1p1.
514    in r1p1.
525    issue is present in r0p0 as well but there is no workaround for that
534    issue is present in r0p0 as well but there is no workaround for that
543    It has been fixed in r1p2.
552    It has been fixed in r1p2.
569    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
573    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
579    in r0p2.
582    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
586    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
590    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
595    r0p0 and r0p1. It has been fixed in r0p2.
606    the CPU. It is fixed in r0p2.
611   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
621    been fixed in r2p0.
625    It has been fixed in r2p0.
629    It has been fixed in r2p0.
633    It has been fixed in r2p0.
657    of the CPU and is fixed in r2p1.
661    of the CPU and is fixed in r2p1.
665    and is fixed in r2p1.
669    of the CPU and is fixed in r2p1.
677    of the CPU and is fixed in r2p1.
681    of the CPU and is fixed in r2p1.
685    of the CPU and is fixed in r2p1.
715    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
718    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
721    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
724    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
727    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
730    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
733    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
736    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
739    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
742    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
745    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
749    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
754    it is fixed in r0p3.
760    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
765    in r0p3.
769    in r0p3.
774    It is fixed in r0p3.
778    in r0p3.
799    CPU. This needs to be enabled only for r1p0, it is fixed in r2p0.
803    is fixed in r2p0.
807    is fixed in r2p0.
811    is fixed in r2p0.
815    in r2p0.
819    CPU, it is fixed in r2p1.
823    CPU, it is fixed in r2p1.
827    CPU, it is fixed in r2p1.
831    in r2p1.
835    CPU, it is fixed in r2p1.
839    in r2p1.
843    CPU, it is fixed in r2p1.
847    CPU, it is fixed in r2p1.
855    CPU, it is fixed in r2p1.
859    CPU, it is fixed in r2p1.
890   is fixed in r1p1.
894   fixed in r1p2.
898   of the CPU, it is fixed in r1p1.
902   of the CPU, it is fixed in r1p1.
906   CPU, it is fixed in r1p2.
910   It is fixed in r1p1.
915   in r1p2.
919   r1p1. It is fixed in r1p2.
923   fixed in r1p2.
927   CPU. It is fixed in r1p2.
943   the CPU. It is fixed in r1p2.
949   This needs to be enabled for revisions r0p0 and is fixed in r0p1.
950   The workaround for this erratum is not implemented in EL3, but the flag can
952   feature is enabled and can assist the Kernel in the process of
956   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
961    in r0p2.
964   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
967   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
970   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
973   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
976   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
979   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
982   CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3.
995   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
1008    r0p2, r0p3 and r1p0, it is fixed in r1p1.
1012    r0p2, it is fixed in r0p3.
1016    in r0p3. The issue is also present in r0p0 and r0p1 but there is no
1021    fixed in r0p3. This issue is also present in r0p0 and r0p1 but there is no
1026    r0p2, r0p3 and r1p0, it is fixed in r1p1.
1030    in r1p1.
1034    r0p3 and r1p0, it is fixed in r1p1. This workaround disables MPMM even if
1039    r0p3 and r1p0, it is fixed in r1p1.
1043    r0p3 and r1p0, it is fixed in r1p1.
1047    r0p3, r1p0 and r1p1. It is fixed in r1p2.
1051    r0p3, r1p0, r1p1, and is fixed in r1p2.
1055    fixed in r1p2.
1059    r0p3, r1p0, r1p1. It is fixed in r1p2.
1063    r0p3, r1p0, r1p1 and r1p2. It is fixed in r1p3.
1089    It is fixed in r0p2.
1095    It is fixed in r1p1.
1099    fixed in r1p1.
1103    fixed in r1p1.
1107    It is fixed in r1p1. This errata also applies to r0p0 but that revision has a
1108    different workaround, and since r0p0 is not used in production hardware it is
1114    in r1p1.
1118    It is fixed in r1p1.
1122    workaround for revision r0p0. It is fixed in r1p1.
1126    It is fixed in r1p1.
1130    and r1p1. It is fixed in r1p2.
1134    r1p1 and r1p2. It is fixed in r1p3.
1152    It is fixed in r0p2.
1156    It is fixed in r0p2.
1160    It is fixed in r0p2.
1164    It is fixed in r0p2.
1168    It is fixed in r0p2.
1196    FEAT_SPE is enabled. It is fixed in r0p1.
1200    It is fixed in r0p1.
1208    It is fixed in r0p2.
1212    It is fixed in r0p2.
1218    in r1p0.
1222    fixed in r1p0.
1226    fixed in r1p0.
1234    fixed in r1p0.
1260    fixed in r1p0.
1264    in r1p0.
1268    in r1p0.
1272    in r1p0.
1297    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1300    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1303    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1306    CPU. This needs to be enabled for revisions r0p0, r1p0 and is fixed in
1311    is fixed in r1p1.
1315    fixed in r1p2.
1319    is fixed in r1p1.
1323    is fixed in r1p1.
1329 Shared Unit) errata. The DSU errata details can be found in the respective Arm
1334 Each erratum is identified by an ``ID``, as defined in the DSU errata notice
1344    workaround results in increased DSU power consumption on idle.
1349    r2p0 it is fixed). However, please note that this workaround results in
1355    please note that this workaround results in increased DSU power consumption
1360    implementations and is fixed in r2p1. The affected r2p0 implementations
1370 -  ``SKIP_A57_L1_FLUSH_PWR_DWN``: This flag enables an optimization in the
1380    in a way most programmers expect, and will most probably result in a
1390    as recommended in section "4.7 Non-Temporal Loads/Stores" of the
1401    level cache(LLC) is present in the system, and that the DataSource field