docs/design/cpu-specific-build-macros.rst

12 vulnerability workarounds should be applied at runtime.
15    `CVE-2017-5715`_. This flag can be set to 0 by the platform if none
28    `CVE-2018-3639`_. This build option should be set to 1 if the target
33    This build option should be set to 1 if the target platform contains at
38    in EL3 FW. This build option should be set to 1 if the target platform contains
42    This build option should be set to 1 if the target platform contains at
46    This build option should be set to 1 if the target platform contains at
55 are applied to each CPU by the reset handler. The errata details can be found
78 for it to specify which errata workarounds should be enabled or not.
86    CPU. This needs to be enabled for all revisions of the CPU.
91    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
94    CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
99    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
102    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
107    CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
112    CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
115    CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
118    CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
121    CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
124    link time to Cortex-A53 CPU. This needs to be enabled for some variants of
129    CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
134    to Cortex-A53 CPU.  This needs to be enabled for some variants of revision
143    workaround in software, so they should be covered anyway.
151    CPU. This needs to be enabled only for revision r0p0 of the CPU.
154    CPU. This needs to be enabled only for revision r0p0 of the CPU.
157    CPU. This needs to be enabled only for revision r0p0 of the CPU.
160    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
163    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
166    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
174    CPU. This needs to be enabled only for revision r0p0 of the CPU.
177    CPU. This needs to be enabled only for revision r0p0 of the CPU.
180    CPU. This needs to be enabled only for revision r0p0 of the CPU.
183    CPU. This needs to be enabled only for revision r0p0 of the CPU.
186    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
189    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
192    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
195    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
198    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
201    CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
204    CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
212    CPU. This needs to be enabled only for revision r0p0 of the CPU, and is fixed
216    CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU and
225    CPU. This needs to be enabled r0p0, r1p0, r1p1 revisions of the CPU and is still
231    CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
239    CPU. This needs to be enabled only for revision r0p0 of the CPU.
242    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
247    CPU. This needs to be enabled only for revision r0p0 of the CPU.
250     CPU. This needs to be enabled only for revision r0p0 of the CPU.
255    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
258    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
261    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
264    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
267    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
270    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
273    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
276    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
284    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
287    CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
290    CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
296    CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is
300    CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is
304    CPU. This needs to be enabled for revision r0p0 and r1p0 of the CPU and it is
308    CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is
312    CPU. This needs to be enabled for all revisions <= r1p1 of the CPU and is
318    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
321    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
324    CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
327    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
330    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
333     CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
336     CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
341    CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
344    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
347    CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
351    CPU. This needs to be enabled for revisions r0p0 and r1p0.
354    CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
357    CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
361    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
365    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
370    interconnect IP. This needs to be enabled for revisions r0p0, r1p0, r1p1
374    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
378    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
382    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
388    Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
392   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
396   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
400   Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
405   an ARM interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and
411   Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
415   Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
419   Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
423   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
427   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
431   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
436   an ARM interconnect IP. This needs to be enabled for revisions r0p1 and r0p2
440   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
444   Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
448   Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
454    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
457    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
460    CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
465    CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
468    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
471    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
474    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
477    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
480    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
483    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
486    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
489    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
492    CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
495    CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
498    CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
501    CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
505    CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
509    CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
515    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
519    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
523    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
527    CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
531    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
534    CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
538    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
543    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
547    CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
552    CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of
556    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
560    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
565    interconnect IP. This needs to be enabled for revisions r0p0, r1p0 and r1p1.
569    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
573    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the
577    CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
583    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
587    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
592    IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
596    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
600    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
604    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
608    CPU, this affects all configurations. This needs to be enabled for revisions
612    CPU. This needs to be enabled for revision r0p0 - r0p2 and is still open.
615    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 and is
619    CPU. This needs to be enabled only for revisions r0p0 and r0p1 of
623    CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of
627    CPU. This needs to be enabled only for revisions r0p0, r0p1, r0p2 of
633   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
636   CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and is
640   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
644   CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and
648   CPU. This needs to be enabled for revisions r0p0 and r0p1 of the CPU and
652   CPU. This needs to be enabled for revision r0p1 of the CPU and is fixed in
656   CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and
660   CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU and
666    Cortex-A710 CPU. This needs to be enabled only for revision r1p0. It has
670    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
674    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
678    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
682    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
686    Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
690    Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
694    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
698    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
702    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
706    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
710    Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
714    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
718    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
722    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
726    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
730    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
735    interconnect IP. This needs to be enabled for r0p0, r1p0, r2p0 and r2p1 and
739    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
743    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
747    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
751    Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
755   CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0, r2p1 of the
761    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
764    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
767    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
770    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
773    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3 of the
777    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
780    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
783    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
786    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
789    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
792    CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
795    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
799    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
803    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU,
807    CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
810    CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
814    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
818    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
823    interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
827    CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
831    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
835    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
839    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
843    CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is
849    CPU. This needs to be enabled for revisions r0p0 and r0p1 and is still open.
852    CPU. This needs to be enabled for revisions r0p0 and is still open.
857    CPU. This needs to be enabled only for r1p0, it is fixed in r2p0.
860    CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
864    CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
868    CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
872    CPU. This needs to be enabled only for revision r1p0 of the CPU, it is fixed
876    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
880    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
884    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
888    CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
892    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
896    CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
900    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
904    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
908    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
912    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
916    CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
921    This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 and is
925    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
929    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
933    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
937    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
941    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
945    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
949    CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
955   CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
959   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
963   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
967   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
971   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
975   CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
980   IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
984   Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
988   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is
992   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
996   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
1000   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
1004   CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
1008   CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of
1012   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
1016   CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
1023   This needs to be enabled for revisions r0p0 and is fixed in r0p1.
1025   be enabled/disabled at the platform level. The flag is used when the errata ABI
1030   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
1034    CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
1038   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1041   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1044   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1047   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1050   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1053   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1056   CPU. This needs to be enabled for revision r0p2. It is fixed in r0p3.
1059   CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 and r0p3.
1063   CPU. This needs to be enabled for revision r0p0, r0p1, r0p2 and r0p3.
1069   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
1072   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
1075   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
1078   CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
1081   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1084   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1087   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1090   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
1093   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open.
1098    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
1102    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
1106    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
1110    Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
1115    Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is
1120    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
1124    Cortex-A510 CPU. This needs to be enabled only for revision r1p0 and is fixed
1128    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
1133    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
1137    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
1141    Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
1157    Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
1161    Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3,
1165    Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3,
1169    Cortex-A510 CPU. This needs to be applied to revisions r0p1, r0p2, r0p3,
1179    Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1183    Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1189    Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0.
1193    Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is
1197    Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is
1201    Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
1207    Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and
1212    Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
1216    Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no
1220    Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
1224    Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
1228    Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0,
1232    Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0,
1236    Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0,
1240    Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0,
1246    Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1250    Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1254    Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1258    Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1262    Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1266    Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
1270    Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
1274    Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1
1280    Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0 and r0p1. It
1284    to Cortex-A720_AE CPU. This needs to be enabled for revisions r0p0.
1290    Cortex-A725 CPU. This needs to be enabled for revisions r0p0 when
1294    Cortex-A725 CPU. This needs to be enabled for revisions r0p0.
1298    Cortex-A725 CPU. This needs to be enabled for revisions r0p0, r0p1
1302    Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1306    Cortex-A725 CPU. This needs to be enabled for revisions r0p0 and r0p1.
1312    C1-Ultra CPU. This needs to be enabled for revision r0p0 and is fixed
1316    C1-Ultra CPU. This needs to be enabled for revision r0p0 and is
1320    C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and
1324    C1-Ultra CPU. This needs to be enabled for revision r0p0 and is
1328    C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and
1332    C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and
1336    C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and
1340    C1-Ultra CPU. This needs to be enabled for revision r1p0 and is still
1344    C1-Ultra CPU. This needs to be enabled for revisions r0p0 and r1p0 and
1350    C1-Premium CPU. This needs to be enabled for revision r0p0, and is
1354    C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed
1358    C1-Premium CPU. This needs to be enabled for revision r0p0, and is fixed
1362    C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and
1366    C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and
1370    C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and
1374    C1-Premium CPU. This needs to be enabled for revision r1p0 and is
1378    C1-Premium CPU. This needs to be enabled for revisions r0p0, r1p0 and
1384    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1387    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1390    CPU. This needs to be enabled only for revision r0p0 and is fixed in r1p0.
1393    CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it
1397    CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 and is
1401    CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it
1405    CPU. This needs to be enabled for revisions r0p0 and r1p0 of the CPU, it
1411    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1415    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1419    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1423    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1427    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1431    C1-Nano CPU. This needs to be enabled for revision r0p0 and is fixed
1435    C1-Nano CPU. This needs to be enabled for revisions r0p0 and r0p1, and
1442 Shared Unit) errata. The DSU errata details can be found in the respective Arm
1481 architecture that can be enabled by the platform as desired.
1497    flag enforces this behaviour. This needs to be enabled only for revisions
1501    ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be