Lines Matching refs:lower

27 to preserve the state of the CPU at the next lower exception level (EL) in a given
76 1. **EL3 should only initialize immediate used lower EL**
79 immediate used lower EL. This implies that, when S-EL2 is present in the system,
102 for lower exception levels.
241 corresponding registers from lower exception levels. Because debug and
453 lower exception levels of Secure and Realm worlds. In this scenario, we save the
454 general purpose and Pauth registers while we enter EL3 from lower ELs via
455 ``prepare_el3_entry`` and restore them back while we exit EL3 to lower ELs
526 values to lower exception levels when traps occur. The cached values stored in
543 lower exception levels NS(EL2/EL1) will carry forward those values to EL3.
552 registers configured for lower exception levels.