Lines Matching defs:new_spsr

117 	u_register_t new_spsr = 0;
123 		new_spsr |= (SPSR_M_AARCH64 << SPSR_M_SHIFT) | SPSR_M_EL2H;
126 		new_spsr |= (SPSR_M_AARCH64 << SPSR_M_SHIFT) | SPSR_M_EL1H;
130 	new_spsr |= SPSR_DAIF_MASK << SPSR_DAIF_SHIFT;
133 	new_spsr |= old_spsr & (SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
135 		new_spsr &= ~(SPSR_BTYPE_MASK_AARCH64 << SPSR_BTYPE_SHIFT_AARCH64);
139 	new_spsr |= old_spsr & SPSR_SSBS_BIT_AARCH64;
142 			new_spsr |= SPSR_SSBS_BIT_AARCH64;
144 			new_spsr &= ~SPSR_SSBS_BIT_AARCH64;
149 	new_spsr |= old_spsr & SPSR_ALLINT_BIT_AARCH64;
152 			new_spsr &= ~SPSR_ALLINT_BIT_AARCH64;
154 			new_spsr |= SPSR_ALLINT_BIT_AARCH64;
159 	new_spsr &= ~SPSR_IL_BIT;
162 	new_spsr &= ~SPSR_SS_BIT;
165 	new_spsr |= old_spsr & SPSR_PAN_BIT;
169 	    new_spsr |= SPSR_PAN_BIT;
173 	new_spsr |= old_spsr & SPSR_UAO_BIT_AARCH64;
175 		new_spsr &= ~SPSR_UAO_BIT_AARCH64;
179 	new_spsr |= old_spsr & SPSR_DIT_BIT;
182 	new_spsr |= old_spsr & SPSR_TCO_BIT_AARCH64;
184 		new_spsr |= SPSR_TCO_BIT_AARCH64;
188 	new_spsr |= old_spsr & SPSR_NZCV;
191 	new_spsr |= old_spsr & SPSR_UINJ_BIT;
194 	new_spsr |= old_spsr & SPSR_PM_BIT_AARCH64;
196 		new_spsr |= SPSR_PM_BIT_AARCH64;
200 	new_spsr |= old_spsr & SPSR_PPEND_BIT;
202 		new_spsr &= ~SPSR_PPEND_BIT;
206 	new_spsr |= old_spsr & SPSR_EXLOCK_BIT_AARCH64;
214 		new_spsr |= (gcscr & GCSCR_EXLOCK_EN_BIT) ? SPSR_EXLOCK_BIT_AARCH64 : 0;
218 	new_spsr |= old_spsr & SPSR_PACM_BIT_AARCH64;
220 		new_spsr &= ~SPSR_PACM_BIT_AARCH64;
223 	return new_spsr;
241 	u_register_t new_spsr = 0U;
244 		new_spsr = old_spsr | SPSR_UINJ_BIT;
245 		write_ctx_reg(state, CTX_SPSR_EL3, new_spsr);
266 	new_spsr = create_spsr(old_spsr, to_el);
268 	write_ctx_reg(state, CTX_SPSR_EL3, new_spsr);