Lines Matching refs:sp
104 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
106 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
108 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
110 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
113 str x30, [sp, #CTX_EL3STATE_OFFSET + CTX_NESTED_EA_FLAG]
120 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
130 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
132 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ELR_EL3]
133 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
135 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_SPSR_EL3]
136 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
138 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_ESR_EL3]
146 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
147 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_SAVED_GPREG_LR]
151 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
152 str xzr, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
243 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
251 stp x2, x3, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
259 str x5, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]
271 mov x3, sp
275 ldr x5, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
277 mov sp, x5
282 mov x28, sp
292 mov x27, sp
301 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_DOUBLE_FAULT_ESR]