Lines Matching full:4
24 #define MUX_ID_SHIFT 4
34 #define CLK_DIV_MASK GENMASK_32(9, 4)
35 #define CLK_DIV_SHIFT 4
43 #define DIV_PLL3DIVP 4
87 #define MUX_PLL3 4
168 #define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4)
175 #define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4)
208 #define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4)
214 #define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4)
220 #define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4)
227 #define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4)
233 #define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4)
240 #define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4)
247 #define CLK_UART35_HSE CLKSRC(MUX_UART35, 4)
253 #define CLK_UART4_HSE CLKSRC(MUX_UART4, 4)
259 #define CLK_UART6_HSE CLKSRC(MUX_UART6, 4)
265 #define CLK_UART78_HSE CLKSRC(MUX_UART78, 4)
271 #define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4)
278 #define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4)
284 #define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4)
290 #define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4)
297 #define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4)
303 #define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4)