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1 /* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
36 #define CLK_SEL_MASK GENMASK_32(3, 0)
42 #define DIV_PLL2DIVR 3
86 #define MUX_PLL12 3
137 #define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3)
146 #define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3)
162 #define CLK_RTC_HSE CLKSRC(MUX_RTC, 3)
167 #define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3)
174 #define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3)
182 #define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3)
187 #define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3)
192 #define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3)
197 #define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3)
202 #define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3)
207 #define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3)
213 #define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3)
219 #define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3)
226 #define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3)
232 #define CLK_UART1_CSI CLKSRC(MUX_UART1, 3)
239 #define CLK_UART2_CSI CLKSRC(MUX_UART2, 3)
246 #define CLK_UART35_CSI CLKSRC(MUX_UART35, 3)
252 #define CLK_UART4_CSI CLKSRC(MUX_UART4, 3)
258 #define CLK_UART6_CSI CLKSRC(MUX_UART6, 3)
264 #define CLK_UART78_CSI CLKSRC(MUX_UART78, 3)
270 #define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3)
277 #define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3)
283 #define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3)
289 #define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3)
296 #define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3)
302 #define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3)
309 #define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3)
326 #define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3)
331 #define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3)
349 #define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3)
354 #define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3)
359 #define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3)
367 #define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3)
372 #define CLK_SAES_LSI CLKSRC(MUX_SAES, 3)
382 #define LSEDRV_HIGHEST 3