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1 /* SPDX-License-Identifier: BSD-2-Clause */
735 #define RCC_HWRSTSCLRR_PADRSTF BIT(2)
752 #define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2)
760 #define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
783 #define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
806 #define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
828 #define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
859 #define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
870 #define RCC_BDCR_LSERDY BIT(2)
888 #define RCC_BDCR_LSERDY_BIT 2
892 #define RCC_BDCR_LSEDRV_WIDTH 2
897 #define RCC_D3DCR_MSIRDY BIT(2)
900 #define RCC_D3DCR_MSIRDY_BIT 2
925 #define RCC_C1CIESETR_HSIRDYIE BIT(2)
942 #define RCC_C1CIFCLRR_HSIRDYF BIT(2)
959 #define RCC_C2CIESETR_HSIRDYIE BIT(2)
976 #define RCC_C2CIFCLRR_HSIRDYF BIT(2)
993 #define RCC_CxCIESETR_HSIRDYIE BIT(2)
1011 #define RCC_CxCIFCLRR_HSIRDYF BIT(2)
1036 #define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
1041 #define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
1054 #define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
1059 #define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
1071 #define RCC_C3CFGR_C3LPEN BIT(2)
1147 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
1152 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
1157 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
1162 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
1167 #define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
1172 #define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0)
1195 #define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
1200 #define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
1205 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
1213 #define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
1224 #define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
1228 #define RCC_VDERAMCFGR_VDERAMLPEN BIT(2)
1232 #define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
1236 #define RCC_SRAM2CFGR_SRAM2LPEN BIT(2)
1240 #define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
1244 #define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
1248 #define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2)
1253 #define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2)
1258 #define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2)
1264 #define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
1271 #define RCC_OSPI2CFGR_OSPI2LPEN BIT(2)
1278 #define RCC_OSPIxCFGR_OSPIxLPEN BIT(2)
1285 #define RCC_FMCCFGR_FMCLPEN BIT(2)
1294 #define RCC_STMCFGR_STMLPEN BIT(2)
1298 #define RCC_ETRCFGR_ETRLPEN BIT(2)
1303 #define RCC_GPIOACFGR_GPIOALPEN BIT(2)
1308 #define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
1313 #define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
1318 #define RCC_GPIODCFGR_GPIODLPEN BIT(2)
1323 #define RCC_GPIOECFGR_GPIOELPEN BIT(2)
1328 #define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
1333 #define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
1338 #define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
1343 #define RCC_GPIOICFGR_GPIOILPEN BIT(2)
1348 #define RCC_GPIOJCFGR_GPIOJLPEN BIT(2)
1353 #define RCC_GPIOKCFGR_GPIOKLPEN BIT(2)
1358 #define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
1364 #define RCC_GPIOxCFGR_GPIOxLPEN BIT(2)
1370 #define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
1375 #define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
1380 #define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
1385 #define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2)
1390 #define RCC_LPDMACFGR_LPDMALPEN BIT(2)
1396 #define RCC_HSEMCFGR_HSEMLPEN BIT(2)
1402 #define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
1407 #define RCC_IPCC2CFGR_IPCC2LPEN BIT(2)
1412 #define RCC_RTCCFGR_RTCLPEN BIT(2)
1417 #define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
1421 #define RCC_BSECCFGR_BSECLPEN BIT(2)
1426 #define RCC_IS2MCFGR_IS2MLPEN BIT(2)
1459 #define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
1463 #define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
1497 #define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
1501 #define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
1535 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
1539 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
1558 #define RCC_TIM1CFGR_TIM1LPEN BIT(2)
1563 #define RCC_TIM2CFGR_TIM2LPEN BIT(2)
1568 #define RCC_TIM3CFGR_TIM3LPEN BIT(2)
1573 #define RCC_TIM4CFGR_TIM4LPEN BIT(2)
1578 #define RCC_TIM5CFGR_TIM5LPEN BIT(2)
1583 #define RCC_TIM6CFGR_TIM6LPEN BIT(2)
1588 #define RCC_TIM7CFGR_TIM7LPEN BIT(2)
1593 #define RCC_TIM8CFGR_TIM8LPEN BIT(2)
1598 #define RCC_TIM10CFGR_TIM10LPEN BIT(2)
1603 #define RCC_TIM11CFGR_TIM11LPEN BIT(2)
1608 #define RCC_TIM12CFGR_TIM12LPEN BIT(2)
1613 #define RCC_TIM13CFGR_TIM13LPEN BIT(2)
1618 #define RCC_TIM14CFGR_TIM14LPEN BIT(2)
1623 #define RCC_TIM15CFGR_TIM15LPEN BIT(2)
1628 #define RCC_TIM16CFGR_TIM16LPEN BIT(2)
1633 #define RCC_TIM17CFGR_TIM17LPEN BIT(2)
1638 #define RCC_TIM20CFGR_TIM20LPEN BIT(2)
1643 #define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
1648 #define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
1653 #define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
1659 #define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
1665 #define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
1671 #define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2)
1677 #define RCC_SPI1CFGR_SPI1LPEN BIT(2)
1682 #define RCC_SPI2CFGR_SPI2LPEN BIT(2)
1687 #define RCC_SPI3CFGR_SPI3LPEN BIT(2)
1692 #define RCC_SPI4CFGR_SPI4LPEN BIT(2)
1697 #define RCC_SPI5CFGR_SPI5LPEN BIT(2)
1702 #define RCC_SPI6CFGR_SPI6LPEN BIT(2)
1707 #define RCC_SPI7CFGR_SPI7LPEN BIT(2)
1712 #define RCC_SPI8CFGR_SPI8LPEN BIT(2)
1718 #define RCC_SPIxCFGR_SPIxLPEN BIT(2)
1724 #define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
1729 #define RCC_USART1CFGR_USART1LPEN BIT(2)
1734 #define RCC_USART2CFGR_USART2LPEN BIT(2)
1739 #define RCC_USART3CFGR_USART3LPEN BIT(2)
1744 #define RCC_UART4CFGR_UART4LPEN BIT(2)
1749 #define RCC_UART5CFGR_UART5LPEN BIT(2)
1754 #define RCC_USART6CFGR_USART6LPEN BIT(2)
1759 #define RCC_UART7CFGR_UART7LPEN BIT(2)
1764 #define RCC_UART8CFGR_UART8LPEN BIT(2)
1769 #define RCC_UART9CFGR_UART9LPEN BIT(2)
1774 #define RCC_USARTxCFGR_USARTxLPEN BIT(2)
1779 #define RCC_UARTxCFGR_UARTxLPEN BIT(2)
1784 #define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
1790 #define RCC_I2C1CFGR_I2C1LPEN BIT(2)
1795 #define RCC_I2C2CFGR_I2C2LPEN BIT(2)
1800 #define RCC_I2C3CFGR_I2C3LPEN BIT(2)
1805 #define RCC_I2C4CFGR_I2C4LPEN BIT(2)
1810 #define RCC_I2C5CFGR_I2C5LPEN BIT(2)
1815 #define RCC_I2C6CFGR_I2C6LPEN BIT(2)
1820 #define RCC_I2C7CFGR_I2C7LPEN BIT(2)
1825 #define RCC_I2C8CFGR_I2C8LPEN BIT(2)
1831 #define RCC_I2CxCFGR_I2CxLPEN BIT(2)
1837 #define RCC_SAI1CFGR_SAI1LPEN BIT(2)
1842 #define RCC_SAI2CFGR_SAI2LPEN BIT(2)
1847 #define RCC_SAI3CFGR_SAI3LPEN BIT(2)
1852 #define RCC_SAI4CFGR_SAI4LPEN BIT(2)
1857 #define RCC_SAIxCFGR_SAIxLPEN BIT(2)
1862 #define RCC_MDF1CFGR_MDF1LPEN BIT(2)
1867 #define RCC_MDF2CFGR_MDF2LPEN BIT(2)
1873 #define RCC_FDCANCFGR_FDCANLPEN BIT(2)
1882 #define RCC_ADC12CFGR_ADC12LPEN BIT(2)
1888 #define RCC_ADC3CFGR_ADC3LPEN BIT(2)
1895 #define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
1907 #define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
1919 #define RCC_ETHxCFGR_ETHxMACLPEN BIT(2)
1931 #define RCC_USB2CFGR_USB2LPEN BIT(2)
1937 #define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
1944 #define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
1951 #define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2)
1958 #define RCC_USB3DRCFGR_USB3DRLPEN BIT(2)
1964 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2)
1971 #define RCC_PCIECFGR_PCIELPEN BIT(2)
1977 #define RCC_USBTCCFGR_USBTCLPEN BIT(2)
1982 #define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2)
1990 #define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2)
1994 #define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2)
1998 #define RCC_STGENCFGR_STGENLPEN BIT(2)
2004 #define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
2010 #define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
2016 #define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
2022 #define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2)
2028 #define RCC_GPUCFGR_GPULPEN BIT(2)
2033 #define RCC_LTDCCFGR_LTDCLPEN BIT(2)
2038 #define RCC_DSICFGR_DSILPEN BIT(2)
2045 #define RCC_LVDSCFGR_LVDSLPEN BIT(2)
2051 #define RCC_CSICFGR_CSILPEN BIT(2)
2056 #define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
2061 #define RCC_CCICFGR_CCILPEN BIT(2)
2066 #define RCC_VDECCFGR_VDECLPEN BIT(2)
2071 #define RCC_VENCCFGR_VENCLPEN BIT(2)
2076 #define RCC_RNGCFGR_RNGLPEN BIT(2)
2081 #define RCC_PKACFGR_PKALPEN BIT(2)
2086 #define RCC_SAESCFGR_SAESLPEN BIT(2)
2091 #define RCC_HASHCFGR_HASHLPEN BIT(2)
2096 #define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
2101 #define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
2106 #define RCC_CRYPxCFGR_CRYPxLPEN BIT(2)
2110 #define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
2114 #define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
2118 #define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
2122 #define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
2126 #define RCC_IWDGxCFGR_IWDGxLPEN BIT(2)
2130 #define RCC_IWDG5CFGR_IWDG5LPEN BIT(2)
2136 #define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
2141 #define RCC_WWDG2CFGR_WWDG2LPEN BIT(2)
2147 #define RCC_VREFCFGR_VREFLPEN BIT(2)
2152 #define RCC_DTSCFGR_DTSLPEN BIT(2)
2159 #define RCC_CRCCFGR_CRCLPEN BIT(2)
2164 #define RCC_SERCCFGR_SERCLPEN BIT(2)
2169 #define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2)
2173 #define RCC_GICV2MCFGR_GICV2MLPEN BIT(2)
2178 #define RCC_I3C1CFGR_I3C1LPEN BIT(2)
2183 #define RCC_I3C2CFGR_I3C2LPEN BIT(2)
2188 #define RCC_I3C3CFGR_I3C3LPEN BIT(2)
2193 #define RCC_I3C4CFGR_I3C4LPEN BIT(2)
2199 #define RCC_I3CxCFGR_I3CxLPEN BIT(2)
2279 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)