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1 /* SPDX-License-Identifier: BSD-2-Clause */
667 #define RCC_HWRSTSCLRR_PADRSTF BIT(2)
690 #define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2)
711 #define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2)
732 #define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2)
751 #define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2)
781 #define RCC_STBYBOOTCR_COLD_CPU2 BIT(2)
792 #define RCC_BDCR_LSERDY BIT(2)
796 #define RCC_BDCR_LSEDRV_WIDTH 2
823 #define RCC_C1CIESETR_HSIRDYIE BIT(2)
839 #define RCC_C1CIFCLRR_HSIRDYF BIT(2)
855 #define RCC_C2CIESETR_HSIRDYIE BIT(2)
871 #define RCC_C2CIFCLRR_HSIRDYF BIT(2)
894 #define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2)
899 #define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2)
912 #define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2)
917 #define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2)
931 #define RCC_OCENSETR_MSION BIT(2)
948 #define RCC_OCENCLRR_MSION BIT(2)
959 #define RCC_OCRDYR_MSIRDY BIT(2)
983 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0)
987 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0)
991 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0)
995 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0)
999 #define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0)
1003 #define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0)
1021 #define RCC_DDRCPCFGR_DDRCPLPEN BIT(2)
1026 #define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2)
1031 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2)
1039 #define RCC_DDRCFGR_DDRCFGLPEN BIT(2)
1049 #define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2)
1053 #define RCC_SRAM1CFGR_SRAM1LPEN BIT(2)
1057 #define RCC_RETRAMCFGR_RETRAMLPEN BIT(2)
1061 #define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2)
1066 #define RCC_OSPI1CFGR_OSPI1LPEN BIT(2)
1073 #define RCC_FMCCFGR_FMCLPEN BIT(2)
1083 #define RCC_STMCFGR_STMLPEN BIT(2)
1087 #define RCC_ETRCFGR_ETRLPEN BIT(2)
1092 #define RCC_GPIOACFGR_GPIOALPEN BIT(2)
1097 #define RCC_GPIOBCFGR_GPIOBLPEN BIT(2)
1102 #define RCC_GPIOCCFGR_GPIOCLPEN BIT(2)
1107 #define RCC_GPIODCFGR_GPIODLPEN BIT(2)
1112 #define RCC_GPIOECFGR_GPIOELPEN BIT(2)
1117 #define RCC_GPIOFCFGR_GPIOFLPEN BIT(2)
1122 #define RCC_GPIOGCFGR_GPIOGLPEN BIT(2)
1127 #define RCC_GPIOHCFGR_GPIOHLPEN BIT(2)
1132 #define RCC_GPIOICFGR_GPIOILPEN BIT(2)
1137 #define RCC_GPIOZCFGR_GPIOZLPEN BIT(2)
1142 #define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2)
1147 #define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2)
1152 #define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2)
1157 #define RCC_IPCC1CFGR_IPCC1LPEN BIT(2)
1161 #define RCC_RTCCFGR_RTCLPEN BIT(2)
1165 #define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2)
1169 #define RCC_BSECCFGR_BSECLPEN BIT(2)
1202 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0)
1206 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0)
1232 #define RCC_TIM1CFGR_TIM1LPEN BIT(2)
1237 #define RCC_TIM2CFGR_TIM2LPEN BIT(2)
1242 #define RCC_TIM3CFGR_TIM3LPEN BIT(2)
1247 #define RCC_TIM4CFGR_TIM4LPEN BIT(2)
1252 #define RCC_TIM5CFGR_TIM5LPEN BIT(2)
1257 #define RCC_TIM6CFGR_TIM6LPEN BIT(2)
1262 #define RCC_TIM7CFGR_TIM7LPEN BIT(2)
1267 #define RCC_TIM8CFGR_TIM8LPEN BIT(2)
1272 #define RCC_TIM10CFGR_TIM10LPEN BIT(2)
1277 #define RCC_TIM11CFGR_TIM11LPEN BIT(2)
1282 #define RCC_TIM12CFGR_TIM12LPEN BIT(2)
1287 #define RCC_TIM13CFGR_TIM13LPEN BIT(2)
1292 #define RCC_TIM14CFGR_TIM14LPEN BIT(2)
1297 #define RCC_TIM15CFGR_TIM15LPEN BIT(2)
1302 #define RCC_TIM16CFGR_TIM16LPEN BIT(2)
1307 #define RCC_TIM17CFGR_TIM17LPEN BIT(2)
1312 #define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2)
1317 #define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2)
1322 #define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2)
1327 #define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2)
1332 #define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2)
1337 #define RCC_SPI1CFGR_SPI1LPEN BIT(2)
1342 #define RCC_SPI2CFGR_SPI2LPEN BIT(2)
1347 #define RCC_SPI3CFGR_SPI3LPEN BIT(2)
1352 #define RCC_SPI4CFGR_SPI4LPEN BIT(2)
1357 #define RCC_SPI5CFGR_SPI5LPEN BIT(2)
1362 #define RCC_SPI6CFGR_SPI6LPEN BIT(2)
1367 #define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2)
1372 #define RCC_USART1CFGR_USART1LPEN BIT(2)
1377 #define RCC_USART2CFGR_USART2LPEN BIT(2)
1382 #define RCC_USART3CFGR_USART3LPEN BIT(2)
1387 #define RCC_UART4CFGR_UART4LPEN BIT(2)
1392 #define RCC_UART5CFGR_UART5LPEN BIT(2)
1397 #define RCC_USART6CFGR_USART6LPEN BIT(2)
1402 #define RCC_UART7CFGR_UART7LPEN BIT(2)
1407 #define RCC_LPUART1CFGR_LPUART1LPEN BIT(2)
1412 #define RCC_I2C1CFGR_I2C1LPEN BIT(2)
1417 #define RCC_I2C2CFGR_I2C2LPEN BIT(2)
1422 #define RCC_I2C3CFGR_I2C3LPEN BIT(2)
1427 #define RCC_SAI1CFGR_SAI1LPEN BIT(2)
1432 #define RCC_SAI2CFGR_SAI2LPEN BIT(2)
1437 #define RCC_SAI3CFGR_SAI3LPEN BIT(2)
1442 #define RCC_SAI4CFGR_SAI4LPEN BIT(2)
1447 #define RCC_MDF1CFGR_MDF1LPEN BIT(2)
1452 #define RCC_FDCANCFGR_FDCANLPEN BIT(2)
1461 #define RCC_ADC1CFGR_ADC1LPEN BIT(2)
1467 #define RCC_ADC2CFGR_ADC2LPEN BIT(2)
1473 #define RCC_ETH1CFGR_ETH1MACLPEN BIT(2)
1485 #define RCC_ETH2CFGR_ETH2MACLPEN BIT(2)
1497 #define RCC_USBHCFGR_USBHLPEN BIT(2)
1502 #define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2)
1508 #define RCC_OTGCFGR_OTGLPEN BIT(2)
1513 #define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2)
1518 #define RCC_STGENCFGR_STGENLPEN BIT(2)
1524 #define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2)
1530 #define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2)
1536 #define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2)
1542 #define RCC_LTDCCFGR_LTDCLPEN BIT(2)
1547 #define RCC_CSICFGR_CSILPEN BIT(2)
1552 #define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2)
1557 #define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2)
1562 #define RCC_RNG1CFGR_RNG1LPEN BIT(2)
1567 #define RCC_RNG2CFGR_RNG2LPEN BIT(2)
1572 #define RCC_PKACFGR_PKALPEN BIT(2)
1577 #define RCC_SAESCFGR_SAESLPEN BIT(2)
1582 #define RCC_HASH1CFGR_HASH1LPEN BIT(2)
1587 #define RCC_HASH2CFGR_HASH2LPEN BIT(2)
1592 #define RCC_CRYP1CFGR_CRYP1LPEN BIT(2)
1597 #define RCC_CRYP2CFGR_CRYP2LPEN BIT(2)
1601 #define RCC_IWDG1CFGR_IWDG1LPEN BIT(2)
1605 #define RCC_IWDG2CFGR_IWDG2LPEN BIT(2)
1609 #define RCC_IWDG3CFGR_IWDG3LPEN BIT(2)
1613 #define RCC_IWDG4CFGR_IWDG4LPEN BIT(2)
1618 #define RCC_WWDG1CFGR_WWDG1LPEN BIT(2)
1623 #define RCC_VREFCFGR_VREFLPEN BIT(2)
1628 #define RCC_DTSCFGR_DTSLPEN BIT(2)
1634 #define RCC_CRCCFGR_CRCLPEN BIT(2)
1639 #define RCC_SERCCFGR_SERCLPEN BIT(2)
1644 #define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2)
1649 #define RCC_I3C1CFGR_I3C1LPEN BIT(2)
1654 #define RCC_I3C2CFGR_I3C2LPEN BIT(2)
1659 #define RCC_I3C3CFGR_I3C3LPEN BIT(2)
1662 #define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0)
1728 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0)