Lines Matching full:15

286 #define RCC_MP_RSTSSETR_SPARE			BIT(15)
302 #define RCC_MP_RSTSCLRR_SPARE			BIT(15)
482 #define RCC_PLL1FRACR_FRACV_MASK		GENMASK_32(15, 3)
491 #define RCC_PLL1CSGR_SSCG_MODE			BIT(15)
518 #define RCC_PLL2FRACR_FRACV_MASK		GENMASK_32(15, 3)
527 #define RCC_PLL2CSGR_SSCG_MODE			BIT(15)
556 #define RCC_PLL3FRACR_FRACV_MASK		GENMASK_32(15, 3)
565 #define RCC_PLL3CSGR_SSCG_MODE			BIT(15)
594 #define RCC_PLL4FRACR_FRACV_MASK		GENMASK_32(15, 3)
603 #define RCC_PLL4CSGR_SSCG_MODE			BIT(15)
700 #define RCC_DDRITFCR_DDRCAXIRST			BIT(15)
811 #define RCC_ETH12CKSELR_ETH2PTPDIV_MASK		GENMASK_32(15, 12)
853 #define RCC_APB1RSTSETR_USART3RST		BIT(15)
872 #define RCC_APB1RSTCLRR_USART3RST		BIT(15)
999 #define RCC_AHB4RSTSETR_TSCRST			BIT(15)
1011 #define RCC_AHB4RSTCLRR_TSCRST			BIT(15)
1063 #define RCC_MP_APB1ENSETR_USART3EN		BIT(15)
1082 #define RCC_MP_APB1ENCLRR_USART3EN		BIT(15)
1148 #define RCC_MP_APB4ENSETR_IWDG2APBEN		BIT(15)
1155 #define RCC_MP_APB4ENCLRR_IWDG2APBEN		BIT(15)
1175 #define RCC_MP_APB5ENSETR_IWDG1APBEN		BIT(15)
1183 #define RCC_MP_APB5ENCLRR_IWDG1APBEN		BIT(15)
1238 #define RCC_MP_AHB4ENSETR_TSCEN			BIT(15)
1241 #define RCC_MP_AHB4ENCLRR_TSCEN			BIT(15)
1361 #define RCC_MP_APB1LPENSETR_USART3LPEN		BIT(15)
1380 #define RCC_MP_APB1LPENCLRR_USART3LPEN		BIT(15)
1444 #define RCC_MP_APB4LPENSETR_IWDG2APBLPEN	BIT(15)
1452 #define RCC_MP_APB4LPENCLRR_IWDG2APBLPEN	BIT(15)
1473 #define RCC_MP_APB5LPENSETR_IWDG1APBLPEN	BIT(15)
1482 #define RCC_MP_APB5LPENCLRR_IWDG1APBLPEN	BIT(15)
1538 #define RCC_MP_AHB4LPENSETR_TSCLPEN		BIT(15)
1541 #define RCC_MP_AHB4LPENCLRR_TSCLPEN		BIT(15)
1688 #define RCC_APB5SECSR_IWDG1SECF			BIT(15)
1716 #define RCC_AHB4SECSR_TSCSECF			BIT(15)
1781 #define RCC_PLLNFRACR_FRACV_MASK		GENMASK_32(15, 3)
1789 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT		15
1790 #define RCC_PLLNCSGR_SSCG_MODE_MASK		BIT(15)