79 static struct tzc_instance tzc;  variable
219 	tzc.base = base;  in tzc_init()
225 	tzc_id = tzc_read_component_id(tzc.base);  in tzc_init()
232 	tzc_build = tzc_read_build_config(tzc.base);  in tzc_init()
233 	tzc.num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) &  in tzc_init()
235 	tzc.addr_width  = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) &  in tzc_init()
237 	tzc.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) &  in tzc_init()
267 	assert(tzc.base && cfg);  in tzc_configure_region()
270 	assert(((cfg->filters >> tzc.num_filters) == 0) &&  in tzc_configure_region()
271 	       (region < tzc.num_regions));  in tzc_configure_region()
278 	assert(((cfg->top <= (UINT64_MAX >> (64 - tzc.addr_width))) &&  in tzc_configure_region()
291 	tzc_write_region_base_low(tzc.base, region, addr_low(cfg->base));  in tzc_configure_region()
292 	tzc_write_region_base_high(tzc.base, region, addr_high(cfg->base));  in tzc_configure_region()
294 	tzc_write_region_top_low(tzc.base, region, addr_low(cfg->top));  in tzc_configure_region()
295 	tzc_write_region_top_high(tzc.base, region, addr_high(cfg->top));  in tzc_configure_region()
298 	tzc_write_region_attributes(tzc.base, region,  in tzc_configure_region()
306 	tzc_write_region_id_access(tzc.base, region, cfg->ns_device_access);  in tzc_configure_region()
313 	if (region >= tzc.num_regions)  in tzc_get_region_config()
316 	cfg->base = reg_pair_to_64(tzc_read_region_base_high(tzc.base, region),  in tzc_get_region_config()
317 				   tzc_read_region_base_low(tzc.base, region));  in tzc_get_region_config()
318 	cfg->top = reg_pair_to_64(tzc_read_region_top_high(tzc.base, region),  in tzc_get_region_config()
319 				  tzc_read_region_top_low(tzc.base, region));  in tzc_get_region_config()
321 	cfg->ns_device_access = tzc_read_region_id_access(tzc.base, region);  in tzc_get_region_config()
323 	val32 = tzc_read_region_attributes(tzc.base, region);  in tzc_get_region_config()
332 	assert(tzc.base);  in tzc_set_action()
339 	tzc_write_action(tzc.base, action);  in tzc_set_action()
348 	assert(tzc.base);  in tzc_enable_filters()
350 	for (filter = 0; filter < tzc.num_filters; filter++) {  in tzc_enable_filters()
351 		state = tzc_get_gate_keeper(tzc.base, filter);  in tzc_enable_filters()
366 		tzc_set_gate_keeper(tzc.base, filter, 1);  in tzc_enable_filters()
375 	assert(tzc.base);  in tzc_disable_filters()
381 	for (filter = 0; filter < tzc.num_filters; filter++)  in tzc_disable_filters()
382 		tzc_set_gate_keeper(tzc.base, filter, 0);  in tzc_disable_filters()
387 	return io_read32(tzc.base + FAIL_CONTROL(filter)) &  in write_not_read()
393 	return io_read32(tzc.base + FAIL_CONTROL(filter)) &  in nonsecure_not_secure()
399 	return io_read32(tzc.base + FAIL_CONTROL(filter)) &  in priv_not_unpriv()
406 	uint32_t status = io_read32(tzc.base + INT_STATUS);  in dump_fail_filter()
422 	addr = reg_pair_to_64(io_read32(tzc.base + FAIL_ADDRESS_HIGH(filter)),  in dump_fail_filter()
423 			      io_read32(tzc.base + FAIL_ADDRESS_LOW(filter)));  in dump_fail_filter()
430 	     io_read32(tzc.base + FAIL_ID(filter)));  in dump_fail_filter()
441 	for (filter = 0; filter < tzc.num_filters; filter++)  in tzc_fail_dump()
447 	assert(tzc.base);  in tzc_int_clear()
449 	io_setbits32(tzc.base + INT_CLEAR, GENMASK_32(tzc.num_filters - 1, 0));  in tzc_int_clear()
469 		temp_32reg = tzc_read_region_attributes(tzc.base, n);  in tzc_dump_state()
474 		temp_32reg = tzc_read_region_base_low(tzc.base, n);  in tzc_dump_state()
475 		temp_32reg_h = tzc_read_region_base_high(tzc.base, n);  in tzc_dump_state()
477 		temp_32reg = tzc_read_region_top_low(tzc.base, n);  in tzc_dump_state()
478 		temp_32reg_h = tzc_read_region_top_high(tzc.base, n);  in tzc_dump_state()
480 		temp_32reg = tzc_read_region_attributes(tzc.base, n);  in tzc_dump_state()
484 		for (filter = 0; filter < tzc.num_filters; filter++)  in tzc_dump_state()