161 	vaddr_t iwdg_base = get_base(iwdg);  in iwdg_wait_sync()  local
163 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)  in iwdg_wait_sync()
167 	if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)  in iwdg_wait_sync()
175 	vaddr_t iwdg_base = get_base(iwdg);  in stm32_iwdg_it_ack()  local
178 		io_setbits32(iwdg_base + IWDG_ICR_OFFSET, IWDG_ICR_EWIC);  in stm32_iwdg_it_ack()
180 		io_setbits32(iwdg_base + IWDG_EWCR_OFFSET, IWDG_EWCR_EWIC);  in stm32_iwdg_it_ack()
187 	vaddr_t iwdg_base = get_base(iwdg);  in stm32_iwdg_it_handler()  local
192 	if (!(io_read32(iwdg_base + IWDG_SR_OFFSET) & sr_ewif_mask(iwdg)))  in stm32_iwdg_it_handler()
200 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_WPROT_KEY);  in stm32_iwdg_it_handler()
221 	vaddr_t iwdg_base = get_base(iwdg);  in configure_timeout()  local
236 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);  in configure_timeout()
237 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_1024);  in configure_timeout()
238 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);  in configure_timeout()
240 	    !(io_read32(iwdg_base + IWDG_EWCR_OFFSET) & IWDG_EWCR_EWIE))  in configure_timeout()
241 		io_write32(iwdg_base + IWDG_EWCR_OFFSET,  in configure_timeout()
246 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);  in configure_timeout()
496 	vaddr_t iwdg_base = get_base(iwdg);  in iwdg_wdt_get_version_and_status()  local
499 	iwdg->hw_version = io_read32(iwdg_base + IWDG_VERR_OFFSET) &  in iwdg_wdt_get_version_and_status()
504 		if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_ONF)  in iwdg_wdt_get_version_and_status()
513 		io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);  in iwdg_wdt_get_version_and_status()
515 		rlr_value = io_read32(iwdg_base + IWDG_RLR_OFFSET);  in iwdg_wdt_get_version_and_status()
516 		io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);  in iwdg_wdt_get_version_and_status()
521 		io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_WPROT_KEY);  in iwdg_wdt_get_version_and_status()