Lines Matching +full:- +full:j
1 // SPDX-License-Identifier: BSD-2-Clause
143 size_t j = 0; in pl022_txrx8() local
147 if (pd->data_size_bits != 8) { in pl022_txrx8()
149 pd->data_size_bits); in pl022_txrx8()
155 if (io_read8(pd->base + SSPSR) & SSPSR_TNF) { in pl022_txrx8()
157 io_write8(pd->base + SSPDR, wdat[i++]); in pl022_txrx8()
161 if (io_read8(pd->base + SSPSR) & SSPSR_RNE) { in pl022_txrx8()
163 rdat[j++] = io_read8(pd->base + SSPDR); in pl022_txrx8()
169 while ((j < num_pkts) && in pl022_txrx8()
170 (io_read8(pd->base + SSPSR) & SSPSR_RNE)) { in pl022_txrx8()
172 rdat[j++] = io_read8(pd->base + SSPDR); in pl022_txrx8()
175 if (j < num_pkts) { in pl022_txrx8()
177 num_pkts, j); in pl022_txrx8()
189 size_t j = 0; in pl022_txrx16() local
192 if (pd->data_size_bits != 16) { in pl022_txrx16()
194 pd->data_size_bits); in pl022_txrx16()
200 if (io_read8(pd->base + SSPSR) & SSPSR_TNF) { in pl022_txrx16()
202 io_write16(pd->base + SSPDR, wdat[i++]); in pl022_txrx16()
206 if (io_read8(pd->base + SSPSR) & SSPSR_RNE) { in pl022_txrx16()
208 rdat[j++] = io_read16(pd->base + SSPDR); in pl022_txrx16()
214 while ((j < num_pkts) && in pl022_txrx16()
215 (io_read8(pd->base + SSPSR) & SSPSR_RNE)) { in pl022_txrx16()
217 rdat[j++] = io_read16(pd->base + SSPDR); in pl022_txrx16()
220 if (j < num_pkts) { in pl022_txrx16()
222 num_pkts, j); in pl022_txrx16()
234 io_read8(pd->base + SSPPeriphID0), in pl022_print_peri_id()
235 io_read8(pd->base + SSPPeriphID1), in pl022_print_peri_id()
236 io_read8(pd->base + SSPPeriphID2), in pl022_print_peri_id()
237 io_read8(pd->base + SSPPeriphID3)); in pl022_print_peri_id()
244 io_read8(pd->base + SSPPCellID0), in pl022_print_cell_id()
245 io_read8(pd->base + SSPPCellID1), in pl022_print_cell_id()
246 io_read8(pd->base + SSPPCellID2), in pl022_print_cell_id()
247 io_read8(pd->base + SSPPCellID3)); in pl022_print_cell_id()
253 assert(pd->chip.ops); in pl022_sanity_check()
254 assert(pd->cs_control <= PL022_CS_CTRL_MANUAL); in pl022_sanity_check()
255 switch (pd->cs_control) { in pl022_sanity_check()
257 assert(pd->cs_data.gpio_data.chip); in pl022_sanity_check()
258 assert(pd->cs_data.gpio_data.chip->ops); in pl022_sanity_check()
261 assert(pd->cs_data.cs_cb); in pl022_sanity_check()
266 assert(pd->clk_hz); in pl022_sanity_check()
267 assert(pd->speed_hz && pd->speed_hz <= pd->clk_hz/2); in pl022_sanity_check()
268 assert(pd->mode <= SPI_MODE3); in pl022_sanity_check()
269 assert(pd->data_size_bits == 8 || pd->data_size_bits == 16); in pl022_sanity_check()
273 io_read8(pd->base + SSPB2BTRANS)); in pl022_sanity_check()
282 return pd->clk_hz / (cpsdvr * (1 + scr)); in pl022_calc_freq()
289 switch (pd->cs_control) { in pl022_control_cs()
291 if (io_read8(pd->base + SSPSR) & SSPSR_BSY) in pl022_control_cs()
292 DMSG("pl022 busy - do NOT set CS!"); in pl022_control_cs()
293 while (io_read8(pd->base + SSPSR) & SSPSR_BSY) in pl022_control_cs()
295 DMSG("pl022 done - set CS!"); in pl022_control_cs()
297 pd->cs_data.gpio_data.chip->ops->set_value(NULL, in pl022_control_cs()
298 pd->cs_data.gpio_data.pin_num, value); in pl022_control_cs()
301 pd->cs_data.cs_cb(value); in pl022_control_cs()
322 if (freq1 == pd->speed_hz) in pl022_calc_clk_divisors()
324 else if (freq1 < pd->speed_hz) in pl022_calc_clk_divisors()
335 if (freq2 <= pd->speed_hz) in pl022_calc_clk_divisors()
345 pd->speed_hz, freq1); in pl022_calc_clk_divisors()
350 pd->speed_hz, freq2); in pl022_calc_clk_divisors()
361 while (io_read32(pd->base + SSPSR) & SSPSR_RNE) { in pl022_flush_fifo()
362 rdat = io_read32(pd->base + SSPDR); in pl022_flush_fifo()
365 } while (io_read32(pd->base + SSPSR) & SSPSR_BSY); in pl022_flush_fifo()
379 switch (pd->cs_control) { in pl022_configure()
383 pd->cs_data.gpio_data.chip->ops->set_interrupt(NULL, in pl022_configure()
384 pd->cs_data.gpio_data.pin_num, in pl022_configure()
387 pd->cs_data.gpio_data.chip->ops->set_direction(NULL, in pl022_configure()
388 pd->cs_data.gpio_data.pin_num, in pl022_configure()
398 EMSG("Invalid CS control type: %d", pd->cs_control); in pl022_configure()
408 switch (pd->mode) { in pl022_configure()
426 EMSG("Invalid SPI mode: %u", pd->mode); in pl022_configure()
430 switch (pd->data_size_bits) { in pl022_configure()
440 EMSG("Unsupported data size: %u bits", pd->data_size_bits); in pl022_configure()
444 if (pd->loopback) { in pl022_configure()
448 DMSG("Starting in regular (non-loopback) mode!"); in pl022_configure()
453 DMSG("Set frame format (SPI) and data size (8- or 16-bit)"); in pl022_configure()
454 io_mask16(pd->base + SSPCR0, SHIFT_U32(scr, 8) | mode | SSPCR0_FRF_SPI | in pl022_configure()
458 io_mask8(pd->base + SSPCR1, SSPCR1_SOD_DISABLE | SSPCR1_MS_MASTER | in pl022_configure()
462 io_mask8(pd->base + SSPCPSR, cpsdvr, SSPCPSR_CPSDVR); in pl022_configure()
465 io_mask8(pd->base + SSPIMSC, 0, MASK_4); in pl022_configure()
468 io_mask8(pd->base + SSPICR, SSPICR_RORIC | SSPICR_RTIC, in pl022_configure()
480 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_ENABLE, SSPCR1_SSE); in pl022_start()
492 io_mask8(pd->base + SSPCR1, SSPCR1_SSE_DISABLE, SSPCR1_SSE); in pl022_end()
508 pd->chip.ops = &pl022_ops; in pl022_init()