152 static void dspi_setup_speed(struct ls_dspi_data *dspi_data,  in dspi_setup_speed()  argument
161 	bus_clock = dspi_data->bus_clk_hz;  in dspi_setup_speed()
166 	bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);  in dspi_setup_speed()
173 		speed = dspi_data->speed_hz;  in dspi_setup_speed()
180 		io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);  in dspi_setup_speed()
181 		dspi_data->speed_hz = speed;  in dspi_setup_speed()
191 static void dspi_tx(struct ls_dspi_data *dspi_data, uint32_t ctrl,  in dspi_tx()  argument
195 	uint32_t dspi_val_addr = dspi_data->base + DSPI_PUSHR;  in dspi_tx()
199 	while (DSPI_SR_TXCTR(io_read32(dspi_data->base + DSPI_SR)) >= 4 &&  in dspi_tx()
213 static uint16_t dspi_rx(struct ls_dspi_data *dspi_data)  in dspi_rx()  argument
216 	uint32_t dspi_val_addr = dspi_data->base + DSPI_POPR;  in dspi_rx()
219 	while (DSPI_SR_RXCTR(io_read32(dspi_data->base + DSPI_SR)) == 0 &&  in dspi_rx()
378 static void dspi_flush_fifo(struct ls_dspi_data *dspi_data)  in dspi_flush_fifo()  argument
382 	mcr_val = io_read32(dspi_data->base + DSPI_MCR);  in dspi_flush_fifo()
386 	io_write32(dspi_data->base + DSPI_MCR, mcr_val);  in dspi_flush_fifo()
407 static void dspi_set_cs_active_state(struct ls_dspi_data *dspi_data,  in dspi_set_cs_active_state()  argument
414 		io_clrbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));  in dspi_set_cs_active_state()
417 		io_setbits32(dspi_data->base + DSPI_MCR, DSPI_MCR_PCSIS(cs));  in dspi_set_cs_active_state()
425 static void dspi_set_transfer_state(struct ls_dspi_data *dspi_data,  in dspi_set_transfer_state()  argument
431 	     dspi_data->slave_data_size_bits);  in dspi_set_transfer_state()
433 	bus_setup = io_read32(dspi_data->base + DSPI_CTAR0);  in dspi_set_transfer_state()
435 	bus_setup |= dspi_data->ctar_val;  in dspi_set_transfer_state()
445 	if (dspi_data->slave_data_size_bits == 8)  in dspi_set_transfer_state()
447 	else if (dspi_data->slave_data_size_bits == 16)  in dspi_set_transfer_state()
450 	if (dspi_data->ctar_sel == 0)  in dspi_set_transfer_state()
451 		io_write32(dspi_data->base + DSPI_CTAR0, bus_setup);  in dspi_set_transfer_state()
453 		io_write32(dspi_data->base + DSPI_CTAR1, bus_setup);  in dspi_set_transfer_state()
461 static void dspi_set_speed(struct ls_dspi_data *dspi_data,  in dspi_set_speed()  argument
464 	dspi_setup_speed(dspi_data, speed_max_hz);  in dspi_set_speed()
474 static void dspi_config_slave_state(struct ls_dspi_data *dspi_data,  in dspi_config_slave_state()  argument
481 	dspi_set_speed(dspi_data, speed_max_hz);  in dspi_config_slave_state()
484 	dspi_set_transfer_state(dspi_data, state);  in dspi_config_slave_state()
487 	dspi_set_cs_active_state(dspi_data, cs, state);  in dspi_config_slave_state()
490 	dspi_flush_fifo(dspi_data);  in dspi_config_slave_state()
493 	sr_val = io_read32(dspi_data->base + DSPI_SR);  in dspi_config_slave_state()
503 static void dspi_set_master_state(struct ls_dspi_data *dspi_data,  in dspi_set_master_state()  argument
507 	io_write32(dspi_data->base + DSPI_MCR, mcr_val);  in dspi_set_master_state()
535 static TEE_Result get_info_from_device_tree(struct ls_dspi_data *dspi_data)  in get_info_from_device_tree()  argument
562 		if (bus_num && dspi_data->slave_bus ==  in get_info_from_device_tree()
573 	dspi_data->base = ctrl_base;  in get_info_from_device_tree()
574 	dspi_data->bus_clk_hz = DSPI_CLK;  in get_info_from_device_tree()
578 		dspi_data->num_chipselect = (int)fdt32_to_cpu(*chip_select_num);  in get_info_from_device_tree()
582 	dspi_data->speed_hz = DSPI_DEFAULT_SCK_FREQ;  in get_info_from_device_tree()
597 TEE_Result ls_dspi_init(struct ls_dspi_data *dspi_data)  in ls_dspi_init()  argument
605 	if (dspi_data)  in ls_dspi_init()
606 		status = get_info_from_device_tree(dspi_data);  in ls_dspi_init()
609 		dspi_data->chip.ops = &ls_dspi_ops;  in ls_dspi_init()