riscv/kernel/entry.S

37 	csrr	t0, CSR_XSCRATCH /* t0: hart_index */
38 	bge	t0, t1, unhandled_cpu
39 	addi	t0, t0, 1
41 	mul	t1, t0, t1
43 	lw	t0, 0(t2)
44 	add	t0, t0, t2
45 	add	sp, t1, t0
50 	csrr	t0, CSR_XSCRATCH
52 	slli	t0, t0, 2
53 	add	t1, t1, t0
61 	csrr	t0, CSR_XSCRATCH /* t0: hart_index */
63 	mul	t2, t1, t0
69 	sw	t0, THREAD_CORE_LOCAL_HART_INDEX(tp)
74 	la	t0, sem_cpu_sync
78 	lw	t1, 0(t0)
85 	la	t0, sem_cpu_sync
91 	addi	t0, t0, 4
94 	lw	t1, 0(t0)
103 		la	t0, sem_cpu_sync_start
154 	lla	t0, __bss_start
156 	beq	t0, t1, 1f
158 	STR	zero, (t0)
159 	add	t0, t0, RISCV_XLEN_BYTES
160 	bne	t0, t1, 0b
163 	lla	t0, _start
165 	STR	t0, (t1)
177 	la	t0, __vcore_free_end
179 	sub	t1, t0, t1
192 	sub	t0, t0, t2
193 	STR	t0, THREAD_CORE_LOCAL_TMP_STACK_VA_END(t1)
195 	sub	t2, t0, t2
201 	mv	sp, t0
210 	li	t0, 1
211 	STR	t0, 0(t2)
267 	la	t0, thread_core_local
268 	STR	tp, 0(t0)
395 	csrr	t0, CSR_XSCRATCH /* t0: hart_index */
399 	mul	t2, t2, t0
402 	sw	t0, THREAD_CORE_LOCAL_HART_INDEX(tp)
439 	la	t0, __rel_dyn_start
441 	beq	t0, t1, 5f
443 	LDR	t5, RISCV_XLEN_BYTES(t0)        /* t5: relocation info:type */
446 	LDR	t3, 0(t0)                       /* t3: offset */
447 	LDR	t5, (RISCV_XLEN_BYTES * 2)(t0)  /* t5: addend */
460 	LDR	t3, 0(t0)
464 	LDR	t6, (RISCV_XLEN_BYTES * 2)(t0)  /* t6: addend */
471 	addi	t0, t0, (RISCV_XLEN_BYTES * 3)
472 	blt	t0, t1, 2b