riscv/kernel/entry.S

124 	csrr	a0, CSR_MHARTID
126 	mv	s0, a0		/* Save hart ID into s0 */
148 	li	a0, 0
220 	STR	a0, THREAD_CORE_LOCAL_ABT_STACK_VA_END(tp)
221 	li	a0, THREAD_ID_INVALID
222 	sh	a0, THREAD_CORE_LOCAL_CURR_THREAD(tp)
223 	li	a0, THREAD_CLF_TMP
224 	sw	a0, THREAD_CORE_LOCAL_FLAGS(tp)
230 	la	a0, __vcore_free_start
241 	li	a0, CFG_CORE_ASLR_SEED
246 	mv	a0, x0
252 	la	a0, boot_mmu_config
253 	LDR	a0, CORE_MMU_CONFIG_MAP_OFFSET(a0)
254 	beqz	a0, 1f		/* no offset, skip dynamic relocation */
276 	la	a0, boot_mmu_config
277 	LDR	a0, CORE_MMU_CONFIG_MAP_OFFSET(a0)
279 	add	a1, a1, a0
282 	add	a1, a1, a0
297 	mv	a0, s1		/* s1 contains saved device tree address */
322 	mul	a2, a2, a0
334 	la	a0, threads
335 	LDR	a0, 0(a0)
336 	LDR	a0, THREAD_CTX_STACK_VA_END(a0)
337 	mv	sp, a0
339 	mv	s3, a0
349 	li	a0, THREAD_CLF_TMP
350 	sw	a0, THREAD_CORE_LOCAL_FLAGS(s3)
356 	mv	a0, sp
376 	li	a0, TEEABI_OPTEED_RETURN_ENTRY_DONE
413 	li	a0, TEEABI_OPTEED_RETURN_ON_DONE
448 	add	t5, t5, a0                      /* t5: add ASLR offset */
467 	add	t5, t5, a0                      /* t5: add ASLR offset */
493 	csrr	a0, CSR_XSCRATCH
498 	mul	a0, a0, a2
499 	add	a1, a1, a0