riscv/kernel/entry.S

65 	LDR	tp, 0(tp)
253 	LDR	a0, CORE_MMU_CONFIG_MAP_OFFSET(a0)
277 	LDR	a0, CORE_MMU_CONFIG_MAP_OFFSET(a0)
278 	LDR	a1, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
281 	LDR	a1, THREAD_CORE_LOCAL_ABT_STACK_VA_END(tp)
309 	LDR	a1, __thread_core_count_new
312 	LDR	a1, __thread_core_local_new
324 	LDR	sp, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
335 	LDR	a0, 0(a0)
336 	LDR	a0, THREAD_CTX_STACK_VA_END(a0)
364 	LDR	s0, 0(sp)
396 	LDR	t1, thread_core_local
403 	LDR	sp, THREAD_CORE_LOCAL_TMP_STACK_VA_END(tp)
443 	LDR	t5, RISCV_XLEN_BYTES(t0)        /* t5: relocation info:type */
446 	LDR	t3, 0(t0)                       /* t3: offset */
447 	LDR	t5, (RISCV_XLEN_BYTES * 2)(t0)  /* t5: addend */
460 	LDR	t3, 0(t0)
464 	LDR	t6, (RISCV_XLEN_BYTES * 2)(t0)  /* t6: addend */
465 	LDR	t5, RISCV_XLEN_BYTES(t5)        /* t5: sym value */
495 	LDR	a3, CORE_MMU_CONFIG_MAP_OFFSET(a1)
500 	LDR	a2, 0(a1)