Lines Matching +full:max +full:- +full:link +full:- +full:speed
4 * Based on xHCI host controller driver in linux-kernel
14 * SPDX-License-Identifier: GPL-2.0+
30 /* Max number of USB devices for any host controller - limit in section 6.1 */
32 /* Section 5.3.3 - MaxPorts */
43 * connect status, over-current status, port speed, and device removable.
44 * connect status and port speed are also sticky - meaning they're in
51 * link state, port power, port indicator state, "wake on" enable state
65 * over-current, reset, link state, and L1 change
69 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
92 /* bits 7:0 - how long is the Capabilities register */
97 /* HCSPARAMS1 - hcs_params1 - bitmasks */
98 /* bits 0:7, Max Device Slots */
101 /* bits 8:18, Max Interrupters */
103 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
108 /* HCSPARAMS2 - hcs_params2 - bitmasks */
112 /* bits 4:7, max number of Event Ring segments */
115 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
119 /* HCSPARAMS3 - hcs_params3 - bitmasks */
120 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
122 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
125 /* HCCPARAMS - hcc_params - bitmasks */
126 /* true: HC can use 64-bit address pointers */
130 /* true: HC uses 64-byte Device Context structures
131 * FIXME 64-byte context structures aren't supported yet.
144 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
146 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
149 /* db_off bitmask - bits 0:1 reserved */
152 /* run_regs_off bitmask - bits 0:4 reserved */
178 /* USBCMD - USB command - command bitmasks */
179 /* start/stop HC execution - do not write unless HC is halted*/
181 /* Reset HC - resets internal HC state machine and all registers (except
186 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
188 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
191 /* light reset (port status stays unchanged) - reset completed when this is 0 */
196 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
198 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
199 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
201 * disabled, or powered-off state.
206 /* USBSTS - USB status - status bitmasks */
207 /* HC not running - set to 1 when run/stop bit is cleared. */
211 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
216 /* save state status - '1' means xHC is saving state */
218 /* restore state status - '1' means xHC is restoring state */
224 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
229 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
240 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
244 /* stop ring immediately - abort the currently executing command */
249 /* Command Ring pointer - bit mask for the lower 32 bits. */
252 /* CONFIG - Configure Register - config_reg bitmasks */
253 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
255 /* bits 8:31 - reserved and should be preserved */
257 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
263 /* true: port has an over-current condition */
267 /* Port Link State - bits 5:8
268 * A read gives the current link PM state of the port,
269 * a write with Link State Write Strobe set sets the link state.
278 /* bits 10:13 indicate device speed:
279 * 0 - undefined speed - port hasn't be initialized by a reset yet
280 * 1 - full speed
281 * 2 - low speed
282 * 3 - high speed
283 * 4 - super speed
284 * 5-15 reserved
296 /* Bits 20:23 in the Slot Context are the speed for the device */
306 /* Port Link State Write Strobe - set this when changing link state */
314 * also resets the link, forcing the device through the link training sequence.
318 /* true: over-current change */
320 /* true: reset change - 1 to 0 transition of PORT_RESET */
322 /* port link status change - set on some port link state transitions:
324 * --------------------------------------------------------------------------
325 * - U3 to Resume Wakeup signaling from a device
326 * - Resume to Recovery to U0 USB 3.0 device resume
327 * - Resume to U0 USB 2.0 device resume
328 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
329 * - U3 to U0 Software resume of USB 2.0 device complete
330 * - U2 to U0 L1 resume of USB 2.1 device complete
331 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
332 * - U0 to disabled L1 entry error with USB 2.1 device
333 * - Any state to inactive Error on USB 3.0 port
336 /* port configure error change - port failed to configure its link partner */
343 /* wake on over-current (enable) */
346 /* true: device is removable - for USB 3.0 roothub emulation */
348 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
351 /* We mark duplicate entries with -1 */
352 #define DUPLICATE_ENTRY ((u8)(-1))
354 /* Port Power Management Status and Control - port_power_base bitmasks */
373 * struct xhci_intr_reg - Interrupt Register Set
374 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
376 * @irq_control: IMOD - Interrupt Moderation Register.
383 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
402 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
413 /* Counter used to count down the time to the next interrupt - HW use only */
421 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
425 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
433 * @microframe_index: MFINDEX - current microframe number
448 * Bits 0 - 7: Endpoint target
449 * Bits 8 - 15: RsvdZ
450 * Bits 16 - 31: Stream ID
467 * @port_info: Port offset, count, and protocol-defined information.
499 * @dev_info: Route string, device speed, hub info, and last valid endpoint
500 * @dev_info2: Max exit latency for device number, root hub port number
504 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
505 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
518 /* Route String - 0:19 */
520 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
523 /* Is this LS/FS device connected through a HS hub? - bit 25 */
525 /* Set if the device is a hub - bit 26 */
527 /* Index of the last valid endpoint context in this device context - 27:31 */
530 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
535 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
547 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
548 * The Slot ID of the hub that isolates the high speed signaling from
549 * this low or full-speed device. '0' if attached to root hub port.
553 * The number of the downstream facing port of the high-speed hub
554 * '0' if the device is not low or full speed.
560 /* USB device address - assigned by the HC */
576 * @ep_info2: information on endpoint type, max packet size, max burst size,
579 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
585 * max payload within an Endpoint Service Interval Time (ESIT).
587 * Endpoint Context - section 6.2.1.2.This assumes the HC uses 32-byte context
588 * structures.If the HC uses 64-byte contexts, there is an additional 32 bytes
596 /* offset 0x14 - 0x1f reserved for HC internal use */
602 * Endpoint State - bits 0:2
603 * 0 - disabled
604 * 1 - running
605 * 2 - halted due to halt condition - ok to manipulate endpoint ring
606 * 3 - stopped
607 * 4 - TRB error
608 * 5-7 - reserved
616 /* Mult - Max number of burtst within an interval, in EP companion desc. */
619 /* bits 10:14 are Max Primary Streams */
621 /* Interval - period between requests to an endpoint - 125u increments. */
632 * Force Event - generate transfer events for all TRBs for this endpoint
650 /* bit 7 is Host Initiate Disable - for disabling stream selection */
660 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
691 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
694 /* 64-bit device addresses; we only write 32-bit addresses */
697 /* TODO: write function to set the 64-bit device DMA address */
705 /* 64-bit buffer address, or immediate data */
719 /* Completion Code - only applicable for some types of TRBs */
732 /* TRB Error - some TRB field is invalid */
734 /* Stall Error - USB device is stalled */
736 /* Resource Error - HC doesn't have memory for that device configuration */
738 /* Bandwidth Error - not enough room in schedule for this dev config */
740 /* No Slots Available Error - HC ran out of device slots */
744 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
750 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
752 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
756 /* Parameter Error - Context parameter is invalid */
758 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
760 /* Context State Error - illegal context state transition requested */
762 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
768 /* Missed Service Error - HC couldn't service an isoc ep within interval */
774 /* Stopped - transfer was terminated by a stop endpoint command */
779 /* Control Abort Error - Debug Capability - control pipe aborted */
781 /* Max Exit Latency Too Large Error */
784 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
786 /* Event Lost Error - xHC has an "internal event overrun condition" */
788 /* Undefined Error - reported when other error codes don't apply */
792 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
800 /* 64-bit segment pointer*/
827 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
828 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
841 /* Port ID - bits 31:24 */
847 /* transfer_len bitmasks - bits 0:16 */
850 /* Interrupter Target - which MSI-X vector to target the completion event at */
858 /* Cycle bit - indicates TRB ownership by HC or HCD */
894 struct xhci_link_trb link; member
922 /* Transfer Ring No-op (not for the command ring) */
951 /* Force Header Command - generate a transaction or link management packet */
953 /* No-op Command - not for transfer rings */
955 /* TRB IDs 24-31 reserved */
969 /* Device Notification Event - device sent function wake notification */
971 /* MFINDEX Wrap Event - microframe counter wrapped */
973 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
974 /* Nec vendor-specific command completion event. */
981 /* Above, but for __le32 types -- can avoid work by swapping constants: */
989 * since the command ring is 64-byte aligned.
993 /* Allow two commands + a link TRB, along with any reserved command TRBs */
994 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1026 /* 64-bit event ring segment address */
1088 /* Rings saved to ensure old alt settings can be re-instated */
1093 /* TODO: copied from ehci.h - can be refactored? */
1107 * Some xHCI implementations may support 64-bit address pointers. Registers
1108 * with 64-bit address pointers should be written to with dword accesses by
1110 * xHCI implementations that do not support 64-bit address pointers will ignore
1149 /* HC not running - set to 1 when run/stop bit is cleared. */
1164 /* bits 7:0 - how long is the Capabilities register */
1171 /* Extended capability IDs - ID 0 reserved */
1177 /* IDs 6-9 reserved */
1179 /* USB Legacy Support Capability - section 7.1.1 */
1183 /* USB Legacy Support Capability - section 7.1.1 */
1187 /* USB Legacy Support Control and Status Register - section 7.1.2 */
1193 /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
1196 /* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
1200 /* start/stop HC execution - do not write unless HC is halted*/
1202 /* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
1204 /* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
1206 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
1272 * xhci_deregister() - Unregister an XHCI controller
1275 * @return 0 if registered, -ve on error
1280 * xhci_register() - Register a new XHCI controller
1285 * @return 0 if registered, -ve on error