include/usb/fotg210.h

13 struct fotg210_regs {  struct
15 	struct {
17 	} hccr;			/* 0x00 - 0x0f: hccr */
18 	struct {
20 	} hcor;			/* 0x10 - 0x33: hcor */
21 	uint32_t rsvd1[3];
22 	uint32_t miscr;	/* 0x40: Miscellaneous Register */
23 	uint32_t rsvd2[15];
25 	uint32_t otgcsr;/* 0x80: OTG Control Status Register */
26 	uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */
27 	uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */
28 	uint32_t rsvd3[13];
29 	uint32_t isr;	/* 0xC0: Global Interrupt Status Register */
30 	uint32_t imr;	/* 0xC4: Global Interrupt Mask Register */
31 	uint32_t rsvd4[14];
33 	uint32_t dev_ctrl;/* 0x100: Device Control Register */
34 	uint32_t dev_addr;/* 0x104: Device Address Register */
35 	uint32_t dev_test;/* 0x108: Device Test Register */
36 	uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */
37 	uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */
38 	uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */
39 	uint32_t rsvd5[2];
40 	uint32_t cxfifo;/* 0x120: CX FIFO Register */
41 	uint32_t idle;	/* 0x124: IDLE Counter Register */
42 	uint32_t rsvd6[2];
43 	uint32_t gimr;	/* 0x130: Group Interrupt Mask Register */
44 	uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */
45 	uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */
46 	uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */
47 	uint32_t gisr;	/* 0x140: Group Interrupt Status Register */
48 	uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */
49 	uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */
50 	uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */
51 	uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */
52 	uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */
53 	uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */
54 	uint32_t rsvd7[1];
55 	uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */
56 	uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */
57 	uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */
58 	uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */
59 	uint32_t fifomap;/* 0x1a8: FIFO Map Register */
60 	uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */
61 	uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */
62 	uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */
63 	uint32_t rsvd8[1];
64 	uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */
65 	uint32_t dma_addr; /* 0x1cc: DMA Address Register */
66 	uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */