Lines Matching +full:0 +full:x01000
24 #define TSEC_SIZE 0x40000
25 #define TSEC_MDIO_OFFSET 0x40000
27 #define TSEC_SIZE 0x01000
28 #define TSEC_MDIO_OFFSET 0x01000
31 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
78 #define TBI_CR 0x00
79 #define TBI_SR 0x01
80 #define TBI_ANA 0x04
81 #define TBI_ANLPBPA 0x05
82 #define TBI_ANEX 0x06
83 #define TBI_TBICON 0x11
86 #define TBICON_CLK_SELECT 0x0020
87 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
88 #define TBIANA_SYMMETRIC_PAUSE 0x0080
89 #define TBIANA_HALF_DUPLEX 0x0040
90 #define TBIANA_FULL_DUPLEX 0x0020
91 #define TBICR_PHY_RESET 0x8000
92 #define TBICR_ANEG_ENABLE 0x1000
93 #define TBICR_RESTART_ANEG 0x0200
94 #define TBICR_FULL_DUPLEX 0x0100
95 #define TBICR_SPEED1_SET 0x0040
98 #define MACCFG1_SOFT_RESET 0x80000000
99 #define MACCFG1_RESET_RX_MC 0x00080000
100 #define MACCFG1_RESET_TX_MC 0x00040000
101 #define MACCFG1_RESET_RX_FUN 0x00020000
102 #define MACCFG1_RESET_TX_FUN 0x00010000
103 #define MACCFG1_LOOPBACK 0x00000100
104 #define MACCFG1_RX_FLOW 0x00000020
105 #define MACCFG1_TX_FLOW 0x00000010
106 #define MACCFG1_SYNCD_RX_EN 0x00000008
107 #define MACCFG1_RX_EN 0x00000004
108 #define MACCFG1_SYNCD_TX_EN 0x00000002
109 #define MACCFG1_TX_EN 0x00000001
111 #define MACCFG2_INIT_SETTINGS 0x00007205
112 #define MACCFG2_FULL_DUPLEX 0x00000001
113 #define MACCFG2_IF 0x00000300
114 #define MACCFG2_GMII 0x00000200
115 #define MACCFG2_MII 0x00000100
117 #define ECNTRL_INIT_SETTINGS 0x00001000
118 #define ECNTRL_TBI_MODE 0x00000020
119 #define ECNTRL_REDUCED_MODE 0x00000010
120 #define ECNTRL_R100 0x00000008
121 #define ECNTRL_REDUCED_MII_MODE 0x00000004
122 #define ECNTRL_SGMII_MODE 0x00000002
125 # define CONFIG_SYS_TBIPA_VALUE 0x1f
130 #define MINFLR_INIT_SETTINGS 0x00000040
132 #define DMACTRL_INIT_SETTINGS 0x000000c3
133 #define DMACTRL_GRS 0x00000010
134 #define DMACTRL_GTS 0x00000008
135 #define DMACTRL_LE 0x00008000
137 #define TSTAT_CLEAR_THALT 0x80000000
138 #define RSTAT_CLEAR_RHALT 0x00800000
140 #define IEVENT_INIT_CLEAR 0xffffffff
141 #define IEVENT_BABR 0x80000000
142 #define IEVENT_RXC 0x40000000
143 #define IEVENT_BSY 0x20000000
144 #define IEVENT_EBERR 0x10000000
145 #define IEVENT_MSRO 0x04000000
146 #define IEVENT_GTSC 0x02000000
147 #define IEVENT_BABT 0x01000000
148 #define IEVENT_TXC 0x00800000
149 #define IEVENT_TXE 0x00400000
150 #define IEVENT_TXB 0x00200000
151 #define IEVENT_TXF 0x00100000
152 #define IEVENT_IE 0x00080000
153 #define IEVENT_LC 0x00040000
154 #define IEVENT_CRL 0x00020000
155 #define IEVENT_XFUN 0x00010000
156 #define IEVENT_RXB0 0x00008000
157 #define IEVENT_GRSC 0x00000100
158 #define IEVENT_RXF0 0x00000080
160 #define IMASK_INIT_CLEAR 0x00000000
161 #define IMASK_TXEEN 0x00400000
162 #define IMASK_TXBEN 0x00200000
163 #define IMASK_TXFEN 0x00100000
164 #define IMASK_RXFEN0 0x00000080
167 #define ATTR_INIT_SETTINGS 0x000000c0
168 #define ATTRELI_INIT_SETTINGS 0x00000000
171 #define TXBD_READY 0x8000
172 #define TXBD_PADCRC 0x4000
173 #define TXBD_WRAP 0x2000
174 #define TXBD_INTERRUPT 0x1000
175 #define TXBD_LAST 0x0800
176 #define TXBD_CRC 0x0400
177 #define TXBD_DEF 0x0200
178 #define TXBD_HUGEFRAME 0x0080
179 #define TXBD_LATECOLLISION 0x0080
180 #define TXBD_RETRYLIMIT 0x0040
181 #define TXBD_RETRYCOUNTMASK 0x003c
182 #define TXBD_UNDERRUN 0x0002
183 #define TXBD_STATS 0x03ff
186 #define RXBD_EMPTY 0x8000
187 #define RXBD_RO1 0x4000
188 #define RXBD_WRAP 0x2000
189 #define RXBD_INTERRUPT 0x1000
190 #define RXBD_LAST 0x0800
191 #define RXBD_FIRST 0x0400
192 #define RXBD_MISS 0x0100
193 #define RXBD_BROADCAST 0x0080
194 #define RXBD_MULTICAST 0x0040
195 #define RXBD_LARGE 0x0020
196 #define RXBD_NONOCTET 0x0010
197 #define RXBD_SHORT 0x0008
198 #define RXBD_CRCERR 0x0004
199 #define RXBD_OVERRUN 0x0002
200 #define RXBD_TRUNCATED 0x0001
201 #define RXBD_STATS 0x003f
251 /* (0x2_n700) */
274 u32 iaddr0; /* Individual Address Register 0 */
283 u32 gaddr0; /* Group Address Register 0 */
295 /* General Control and Status Registers (0x2_n000) */
311 /* Transmit Control and Status Registers (0x2_n100) */
321 /* (0x2_n200) */
329 /* Receive Control and Status Registers (0x2_n300) */
342 /* (0x2_n400) */
347 /* MAC Registers (0x2_n500) */
367 /* (0x2_n600) */
370 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
374 /* Hash Function Registers (0x2_n800) */
379 /* Pattern Registers (0x2_nb00) */
384 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
388 #define TSEC_GIGABIT (1 << 0)